VNH3ASP30-E资料

VNH3ASP30-E

AUTOMOTIVE FULLY INTEGRATED

H-BRIDGE MOTOR DRIVER

TARGET SPECIFICATION

Table 1. General Features

TYPEVNH3ASP30-E

RDS(on)42 mΩ max(per leg)

IOUT30 A

Vccmax41 V

Figure 1. Packages OUTPUT CURRENT: 30A

s 5V LOGIC LEVEL COMPATIBLE INPUTS s UNDERVOLTAGE AND OVERVOLTAGE

SHUT-DOWN

s OVERVOLTAGE CLAMPs THERMAL SHUT DOWN

s CROSS-CONDUCTION PROTECTIONs LINEAR CURRENT LIMITERs VERY LOW STAND-BY POWER CONSUMPTION

s PWM OPERATION UP TO 20 KHzs PROTECTION AGAINST:

LOSS OF GROUND AND LOSS OF VCC

s CURRENT SENSE OUTPUT PROPORTIONAL TO MOTOR CURRENT

s IN COMPLIANCE WITH THE 2002/95/ECEUROPEAN DIRECTIVE

DESCRIPTION

The VNH3ASP30-E is a full bridge motor driverintended for a wide range of automotiveapplications. The device incorporates a dualmonolithic High-Side drivers and two Low-Sideswitches. The High-Side driver switch is designedusing STMicroelectronic’s well known and provenproprietary VIPower™ M0 technology that allowsto efficiently integrate on the same die a truePower MOSFET with an intelligent signal/protection circuitry.

MultiPowerSO-30The Low-Side switches are vertical MOSFETsmanufactured using STMicroelectronic’sproprietary EHD (‘STripFET™’) process. Thethree dice are assembled in MultiPowerSO-30package on electrically isolated leadframes. Thispackage, specifically designed for the harshautomotive environment offers improved thermalperformance thanks to exposed die pads.Moreover, its fully symmetrical mechanical designallows superior manufacturability at board level.The input signals INA and INB can directlyinterface to the microcontroller to select the motordirection and the brake condition. The DIAGA/ENAor DIAGB/ENB, when connected to an externalpull-up resistor, enable one leg of the bridge. Theyalso provide a feedback digital diagnostic signal.The normal condition operation is explained in thetruth table on page 7. The CS pin allows to monitorthe motor current by delivering a currentproportional to its value. The PWM, up to 20KHz,lets us to control the speed of the motor in allpossible conditions. In all cases, a low level stateon the PWM pin will turn off both the LSA and LSBswitches. When PWM rises to a high level, LSA orLSB turn on again depending on the input pinstate.

Table 2. Order Codes

Package

Tube

VNH3ASP30-E

Tape and Reel

VNH3ASP30TR-E

MultiPowerSO-30

Rev. 1

September 2004

1/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

Figure 2. Block DiagramVCCOVERTEMPERATURE AOV + UVOVERTEMPERATURE BCLAMP HSAHSACLAMP HSBHSBDRIVERHSALOGICDRIVERHSBCURRENTLIMITATION AOUTACLAMP LSALSADRIVERLSACURRENTLIMITATION B1/K1/KCLAMP LSBDRIVERLSBOUTBLSBGNDADIAGA/ENAINACSPWMINBDIAGB/ENBGNDBFigure 3. Configuration Diagram (Top View) OUTANcVCCNcINAENA/DIAGANcPWMCSENB/DIAGBINBNcVCCNcOUTB130OUTAHeat Slug3OUTANcGNDAGNDAGNDAOUTANcVCCNcOUTBVCCHeat Slug1OUTBHeat Slug21516GNDBGNDBGNDBNcOUTB2/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

Table 3. Pin Definitions And Functions

Pin No1, 25, 30

2,4,7,12,14,17, 22, 24,293, 13, 23651110

15, 16, 2126, 27, 2818, 19, 20

Symbol

OUTA, Heat Slug2NC

VCC, Heat Slug1ENA/DIAGAINAPWMCSINB

ENB/DIAGB

OUTB, Heat Slug3GNDAGNDB

Function

Source of High-Side Switch A / Drain of Low-Side Switch ANot connected

Drain of High-Side Switches and Power Supply Voltage

Status of High-Side and Low-Side Switches A; Open Drain OutputClockwise InputPWM Input

Output of Current senseCounter Clockwise Input

Status of High-Side and Low-Side Switches B; Open Drain OutputSource of High-Side Switch B / Drain of Low-Side Switch BSource of Low-Side Switch A (*)Source of Low-Side Switch B (*)

Note:(*) GNDA and GNDB must be externally connected together.

Table 4. Pin Functions Description

NameVCC GNDAGNDBOUTAOUTBINAINBPWMENA/DIAGAENB/DIAGBCS

Description

Battery connection.

Power grounds, must always be externally connected together.Power connections to the motor.

Voltage controlled input pins with hysteresis, CMOS compatible. These two pins control the state of the bridge in normal operation according to the truth table (brake to VCC, Brake to GND, clockwise and counterclockwise).

Voltage controlled input pin with hysteresis, CMOS compatible.Gates of Low-Side FETS get modulated by the PWM signal during their ON phase allowing speed control of the motor

Open drain bidirectional logic pins.These pins must be connected to an external pull up resistor. When externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of a High-Side FET or excessive ON state voltage drop across a Low-Side FET), these pins are pulled low by the device (see truth table in fault condition).

Analog current sense output. This output sources a current proportional to the motor current. The information can be read back as an analog voltage across an external resistor.

Table 5. Block Descriptions (see Block Diagram)

NameLOGIC CONTROL

OVERVOLTAGE + UNDERVOLTAGEHIGH SIDE AND LOW SIDE CLAMP VOLTAGE

HIGH SIDE AND LOW SIDE DRIVERLINEAR CURRENT LIMITER

OVERTEMPERATURE PROTECTIONFAULT DETECTION

DescriptionAllows the turn-on and the turn-off of the High Side and the Low Side switches according to the truth table.

Shut-down the device outside the range [5.5V..16V] for the battery voltage.

Protect the High Side and the Low Side switches from the high voltage on the battery line in all configuration for the motor.

Drive the gate of the concerned switch to allow a proper RDS(on) for the leg of the bridge.

Limits the motor current, by reducing the High Side Switch gate-source voltage when short-circuit to ground occurs.

In case of short-circuit with the increase of the junction’s temperature, shuts-down the concerned High Side to prevent its degradation and to protect the die.

Signalize an abnormal behavior of the switches in the half-bridge A or B by pulling low the concerned ENx/DIAGx pin.

3/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

Table 6. Absolute Maximum Rating

SymbolVCCImaxIR IINIENIpwVCSParameterSupply Voltage Maximum Output Current (continuous)Reverse Output Current (continuous)Input Current (INA and INB pins)Enable Input Current (DIAGA/ENA and DIAGB/ENB pins)PWM Input Current Current Sense Maximum VoltageElectrostatic Discharge (R=1.5kΩ, C=100pF)- CS pin- logic pins- output pins: OUTA, OUTB, VCCJunction Operating TemperatureCase Operating TemperatureStorage TemperatureValue+ 4130-30+/- 10+/- 10+/- 10-3/+15245Internally Limited-40 to 150-55 to 150 UnitVAAmAmAmAVkVkVkV°C°C°CVESDTjTcTSTGFigure 4. Current and Voltage ConventionsISIINAIINBIENAIENBINAINBDIAGA/ENADIAGB/ENBPWMIpwGNDVINAVINBVENAVENBVpwIGNDGNDAGNDBVCCVCCOUTAOUTBCSIOUTAIOUTBISENSEVSENSEVOUTBVOUTATable 7. Thermal DataSymbolRthj-case Rthj-amb (*)ParameterThermal resistance junction-case (Per leg)Thermal resistance junction-ambient (MAX) (MAX)Value1.020Unit°C/W°C/WNote:(*) When mounted using the recommended pad size on FR-4 board (see MultiPowerSO-30 Mechanical data).

4/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

ELECTRICAL CHARACTERISTICS

(VCC=9V up to 16V; -40°CSymbolVCC

Parameter

Operating supply voltage

Test Conditions

Off state:

Min5.5

Typ

Max16

UnitV

VCC=13V

IS

Supply Current

On state:

INA=INB=PWM=0; Tj=25°C;

12

30TBD10TBD30601224

0.8

1.135

1.7

µAµAmAmAmΩmΩmΩmΩVµAµAA

INA=INB=PWM=0INA or INB=5V, no PWMINA or INB=5V; PWM=20kHzIOUT=12A; Tj=25°C

IOUT=12A; Tj= - 40 to 150°CIOUT=12A; Tj=25°C

IOUT=12A; Tj= - 40 to 150°CIf=12A

Tj=25°C; VOUTX=ENX=0V;

RONHSRONLSVf

Static High-Side resistanceStatic Low-Side resistanceHigh Side Free-wheeling Diode Forward VoltageHigh Side Off State Output Current (per channel)Dynamic Cross-conductionCurrent

IL(off)

VCC=13VVCC=13V

Tj=125°C; VOUTX=ENX=0V; IOUT=12A (see fig. 9)

IRM

Table 9. Logic Inputs (INA, INB, ENA, ENB)

SymbolVILVIHVIHYSTVICLIINLIINHVDIAG

Parameter

Input Low Level VoltageInput High Level VoltageInput Hysteresis VoltageInput Clamp VoltageInput CurrentInput Current

Enable Output Low Level Voltage

Test Conditions

Normal operation (DIAGX/ENX pin acts as an input pin)

Normal operation (DIAGX/ENX pin acts as an input pin)

Normal operation (DIAGX/ENX pin acts as an input pin)IIN=1mA

IIN=-1mAVIN=1.25 VVIN=3.25 V

Fault operation (DIAGX/ENX pin acts as an output pin); IEN=1mA

Min

Typ

Max1.25

3.250.55.5-1.01

6.3-0.7

7.5-0.3100.4

UnitVVVVVµAµAV

5/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

ELECTRICAL CHARACTERISTICS (continued)Table 10. PWM

SymbolVpwlIpwlVpwhIpwhVpwhhystVpwclCINPWM

Parameter

PWM Low Level VoltagePWM Pin Current

PWM High Level VoltagePWM Pin Current

PWM Hysteresis VoltagePWM Clamp VoltagePWM Pin Input Capacitance

Test ConditionsVpw=1.25VVpw=3.25VIpw = 1 mAIpw = -1 mAVIN =2.5V

Min13.25

10

0.5

VCC+0.3VCC+0.7VCC+1.0-6.0

-4.5

-3.025

Typ

Max1.25

UnitVµAVµAVVVpF

Table 11. Switching (VCC=13V, RLOAD=1Ω)

Symbol

ftd(on)td(off)trtf

Parameter

PWM FrequencyTurn-on Delay TimeTurn-off Delay TimeRise TimeFall Time

Delay Time During Change ofOperating Mode

High Side Free Wheeling Diode Reverse Recovery Time

Test Conditions

Input rise time < 1µs (see fig. 8)Input rise time < 1µs (see fig. 8)(see fig. 7)(see fig. 7)(see fig. 6)(see fig. 9)

300Min0

Typ

Max20250250221800

UnitkHzµsµsµsµsµsns

11600110

tDELtrr

Table 12. Protection And Diagnostic

SymbolVUSDVOVILIMVCLPTTSDTTRTHYST

Parameter

Undervoltage Shut-downUndervoltage ResetOvervoltage Shut-down

High-Side Current LimitationTotal Clamp Voltage (VCC to GND)

Thermal Shut-downTemperature

Thermal Reset TemperatureThermal Hysteresis

Test Conditions

Min

Typ4.7194548175

Max5.5226054200

UnitVVVAV°C°C°C

1630

IOUT=12AVIN = 3.25 V

431501357

15

6/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

ELECTRICAL CHARACTERISTICS (continued)Table 13. Current Sense (9VSymbolK1K2dK1 / K1 (*)dK2 / K2 (*)ISENSEO

Parameter

IOUT/ISENSEIOUT/ISENSE

Analog sense current driftAnalog sense current driftAnalog Sense Leakage Current

Test Conditions

IOUT=30A; RSENSE=700ΩTj= - 40 to 150°C

IOUT=8A; RSENSE=700ΩTj= - 40 to 150°C

IOUT=30A; RSENSE=700ΩTj= - 40 to 150°C

IOUT >8A; RSENSE=700ΩTj= - 40 to 150°C

IOUT=0A; VSENSE=0V; Tj= - 40 to 150°C

Min40003750-8-100

Typ47004700

Max54005650+8+1070

%%µAUnit

Note:(*) Analog sense current drift is deviation of factor K for a given device over (-40°C to 150°C and 9Vvalue measured at Tj=25°C, VCC=13V.

WAVEFORMS AND TRUTH TABLE

Table 14. Truth Table In Normal Operating Conditions

In normal operating conditions the DIAGX/ENX pin isconsidered as an input pin by the device. This pin must beexternally pulled high.

INA1100

INB1010

DIAGA/ENA

1111

DIAGB/ENB

1111

OUTAHHLL

PWM pin usage:

In all cases, a “0” on the PWM pin will turn-off both LSAand LSB switches. When PWM rises back to “1”, LSA orLSB turn on again depending on the input pin state.

OUTBHLHL

CSHigh Imp.ISENSE=IOUT/KISENSE=IOUT/K

Operating modeBrake to VCCClockwise (CW)Counterclockwise

(CCW)

High Imp.Brake to GND

7/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

Figure 5. Typical Application Circuit For Dc To 20KHz PWM OperationVCCReg5V+ 5V3.3K1KDIAGA/ENA1KPWMVCCHSAOUTAHSBOUTBµC1K10KINALSACSLSBM33nF1.5KS100KGDb) N MOSFETIn case of a fault condition the DIAGX/ENX pin is consid-ered as an output pin by the device.The fault conditions are:

- overtemperature on one or both high sides (for example if a short to ground occurs as it could be the case described in line 1 and 2 in the table below);

- short to battery condition on the output (saturation detection on the Low-Side Power MOSFET).Possible origins of fault conditions may be:OUTA is shorted to ground ---> overtemperaturedetection on high side A.

OUTA is shorted to VCC ---> Low-Side Power MOSFETsaturation detection.

When a fault condition is detected, the user can knowwhich power element is in fault by monitoring the INA,INB, DIAGA/ENA and DIAGB/ENB pins. In any case,when a fault is detected, the faulty leg of the bridge islatched off. To turn-on the respective output (OUTX)again, the input signal must rise from low to high level.

Table 15. Truth Table In Fault Conditions (detected on OUTA)

INA1100XXXINB1010X10DIAGA/ENA0000000DIAGB/ENB1111011OUTAOPENOPENOPENOPENOPENOPENOPENOUTBHLHLOPENHLCSHigh Imp.High Imp.IOUTB/KHigh Imp.High Imp.IOUTB/KHigh Imp.Fault InformationProtection Action

8/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

Table 16. Electrical Transient Requirements

ISO T/R7637/1Test Pulse

123a3b45ISO T/R7637/1Test Pulse

123a3b45ClassCE

Test Level

I-25V+25V-25V+25V-4V+26.5V

Test Level

II-50V+50V-50V+50V-5V+46.5V

Test Level

III-75V+75V-100V+75V-6V+66.5V

Test Level

IV-100V+100V-150V+100V-7V+86.5V

Test Levels Result

IIICCCCCE

Test LevelsDelays and Impedance

2ms, 10Ω0.2ms, 10Ω0.1µs, 50Ω0.1µs, 50Ω100ms, 0.01Ω400ms, 2ΩTest Levels Result

IVCCCCCE

Test Levels Result

ICCCCCC

Test Levels Result

IICCCCCE

Contents

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.

Reverse Battery Protection

Three possible solutions can be thought of:a) a Schottky diode D connected to VCC pin

b) a N-channel MOSFET connected to the GNDpin (see Typical Application Circuit on fig. 5)

c) a P-channel MOSFET connected to the VCCpin.

The device sustains no more than -30A in reversebattery conditions because of the two Body diodesof the Power MOSFETs. Additionally, in reversebattery condition the I/Os of VNH3ASP30 will bepulled down to the VCC line (approximately -1.5V).Series resistor must be inserted to limit the currentsunk from the microcontroller I/Os. If IRmax is themaximum target reverse current through µC I/Os,series resistor is:

V–VIOsCC

R=---------------------------------I

Rmax

9/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

Figure 6. Definition Of The Delay Times Measurement

VINA,tVINBtPWMtILOADtDELtDELtFigure 7. Definition Of The Low Side Switching Times

PWMtVOUTA, B90%80%tf20%10%trt10/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

Figure 8. Definition Of The High Side Switching Times

VINA,tD(on)tD(off)tVOUTA90%10%tFigure 9. Definition Of Dynamic Cross Conduction Current During A PWM Operation

INA=1, INB=0

PWMtIMOTORtVOUTBtICCIRMttrr11/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

Figure 10. Waveforms in full bridge operationDIAGA/ENADIAGB/ENBINAINBPWMOUTAOUTBIOUTA->OUTBCS (*)NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1)LOAD CONNECTED BETWEEN OUTA, OUTBtDEL(*) CS BEHAVIOUR DURING PWM MODE WILL DEPEND ON PWM FREQUENCY AND DUTY CYCLEtDELNORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)LOAD CONNECTED BETWEEN OUTA, OUTBDIAGA/ENADIAGB/ENBINAINBPWMOUTAOUTBIOUTA->OUTBCS CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUNDINAINBILIMIOUTA->OUTBTTSDTTRTjDIAGA/ENADIAGB/ENBCSnormal operationTj > TTROUTA shorted to groundnormal operation12/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

Figure 11. Waveforms In Full Bridge Operation (continued)OUTA shorted to VCC and undervoltage shutdownINAINBOUTAOUTBIOUTA->OUTBDIAGB/ENBDIAGA/ENACSV元器件交易网www.cecb2b.com

VNH3ASP30-E

Figure 12. Half-bridge ConfigurationThe VNH3ASP30-E can be used as a high power half-bridge driver achieving an ON resistance per leg of 22.5mΩ. Suggested configuration is the following:VCCINAINBDIAGA/ENADIAGB/ENBPWMOUTAOUTBINAINBDIAGA/ENADIAGB/ENBPWMMOUTAOUTBGNDAGNDBGNDAGNDBFigure 13. Multi-motors ConfigurationThe VNH3ASP30-E can easily be designed in multi-motors driving applications such as seat positioning systems where only one motor must be driven at a time. DIAGX/ENX pins allow to put unused half-bridges in high impedance. Suggested configuration is the following:VCCINAINBDIAGA/ENADIAGB/ENBPWMOUTAOUTBINAINBDIAGA/ENADIAGB/ENBPWMM2OUTAOUTBGNDAGNDBGNDAGNDBM1M314/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

PACKAGE MECHANICAL

Table 17. MultiPowerSO-30 Mechanical Data

Symbol

AA2A3BCDEE1eF1F2F3LNS

0deg5.554.69.60.81.8500.420.2317.118.8515.9

161

6.055.110.11.1510deg7deg

17.2millimeters

Min.

Typ

Max.2.352.250.10.580.3217.319.1516.1

Figure 14. MultiPowerSO-30 Package Dimensions15/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

Figure 15. MultiPowerSO-30 Suggested Pad Layout16/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

REVISION HISTORY

DateRevisionSep. 20041- First issue.

Description of Changes

17/18

元器件交易网www.cecb2b.com

VNH3ASP30-E

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grantedby implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subjectto change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are notauthorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.All other names are the property of their respective owners

© 2004 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

18/18