元器件交易网www.cecb2b.comMOTOROLASEMICONDUCTOR TECHNICAL DATAOrder this documentby MCMPC32T/DAdvance Information256K/512K Pipelined BurstRAM™Secondary Cache Modulefor Pentium™The MCMPC32T (256K) and MCMPCT (512K) are designed to pro-vide a burstable, high performance, L2 cache for the Pentium microprocessor inconjunction with Intel’s Triton II chip set. The MCMPC32T is configured as 32Kx bits and the MCMPCT is configured as K x bits. Both are pack-aged in a 160 pin card edge memory module. Each module uses Motorola’s 3.3V 32K x 32 BurstRAMs and one Motorola 3.3 V 32K x 8 FSRAM for the tag RAM.Bursts can be initiated with either address status processor (ADSP) or cacheaddress status (CADS). Subsequent burst addresses are generated internal tothe BurstRAM by the cache burst advance (CADV) input pin.Write cycles are internally self timed and are initiated by the rising edge of theclock (CLK0) input. Eight write enables are provided for byte write control.PD0 – PD3 map into the Triton II chip set for auto–configuration of the cachecontrol.••••••••••••••••Pentium–Style Burst Counter on ChipPipelined Data Out160 Pin Card Edge ModuleAddress Pipeline Supported by ADSP Disabled with ExAll Cache Data and Tag I/Os are TTL CompatibleThree State OutputsByte Write CapabilityFast Module Clock Rate: 66 MHzFast SRAM Access Times:15 ns for Tag RAM8 ns for Data RAMs1.5 Cycle Deselect Data RAMsDecoupling Capacitors for Each Fast Static RAMHigh Quality Multi–Layer FR4 PWB with Separate Power and GroundPlanesSingle 3.3 V +10%, – 5% Power SupplyBurndy Connector, Part Number: CELP2X80SC3Z48Intel COAST 3.0 Option III CompliantBurst Order Select (BOSEL) OptionMCMPC32TMCMPCT160–LEAD CARD EDGECASE TBD, TOP VIEW1424380BurstRAM is a trademark of Motorola.Pentium is a trademark of Intel Corp.This document contains information on a new product. Specifications and information herein are subject to change without notice.1/22/97© Motorola, Inc. 1997MOTOROLA FAST SRAMMCMPC32T•MCMPCT1元器件交易网www.cecb2b.comMCMPC32T BLOCK DIAGRAM32K x 8TIO0 – TIO7TWEA3 – A1813DQ0 – DQ7WA0 – A12A13A14GEECS2ECS115ADSPCADSCADVCLK0CGBWEGWECWE0 – CWE332K x 32SA0 – SA14ADSPADSCADVKGSWSGWSBa – SBdDQ0 – DQ31DQ0 – DQ31SE1SE2SE3LBOZZCCSVDDVDDBOSEL4.7 kΩ1532K x 32SA0 – SA14ADSPADSCADVKGSWSGWSE1SE2SE3LBOZZCWE4 – CWE7SBa – SBdDQ0 – DQ31DQ32 – DQ63MCMPC32T•MCMPCT2MOTOROLA FAST SRAM元器件交易网www.cecb2b.comMCMPCT BLOCK DIAGRAM32K x 8TIO0 – TIO7TWEA3 – A17A1815CCS13DQ0 – DQ7WA0 – A12A13A14GE32K x 32ADSPCADSCADVCLK0CGBWEGWECWE0 –CWE3SA0 – SA14ADSPADSCADVKGSWSGWSBa – SBdDQ0 – DQ31SE1SE2SE3LBOZZ1532K x 32SA0 – SA14ADSPADSCADVKGSWSGWSBa – SBdDQ0 – DQ31DQ0 – DQ31SE1SE2SE3LBOZZVDDVDD4.7 kΩCLK1BOSEL32K x 32SA0 – SA14ADSPADSCADVKGSWSGWCWE4 –CWE7SBa – SBdDQ0 – DQ31SE1SE2SE3LBOZZ32K x 32SA0 – SA14ADSPADSCADVKGSWSGWSBa – SBdDQ0 – DQ31DQ32 –DQ63SE1SE2SE3LBOZZVDDMOTOROLA FAST SRAMMCMPC32T•MCMPCT3元器件交易网www.cecb2b.comPIN ASSIGNMENT160–LEAD CARD EDGE MODULE(DIMM)TOP VIEWVSSTIO1TIO7TIO5TIO3NCVDD5NCCADVVSSCGCWE5CWE7CWE1VDD5CWE3NCNCVSSRSVDA4A6A8A10VDD5A17VSSA9A14A15RSVDPD0PD2BOSELVSSCLK0VSSDQ63VDD5DQ61DQ59DQ57VSSDQ55DQ53DQ51DQ49VSSDQ47DQ45DQ43VDD5DQ41DQ39DQ37VSSDQ35DQ33DQ31VDD5DQ29DQ27DQ25VSSDQ23DQ21DQ19VDD5DQ17DQ15DQ13VSSDQ11DQ9DQ7VDD5DQ5DQ3DQ1VSS818283848586878091929394959697991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601234567101112131415161718192021222324252627282930313233343536373839404142434445474849505152535455565758596061626365666768697071727374757677787980VSSTIO0TIO2TIO6TIO4NCVDD3TWECADSVSSCWE4CWE6CWE0CWE2VDD3CCSGWEBWEVSSA3A7A5A11A16VDD3A18VSSA12A13ADSPECS1ECS2PD1PD3VSSCLK1VSSDQ62VDD3DQ60DQ58DQ56VSSDQ54DQ52DQ50DQ48VSSDQ46DQ44DQ42VDD3DQ40DQ38DQ36VSSDQ34DQ32DQ30VDD3DQ28DQ26DQ24VSSDQ22DQ20DQ18VDD3DQ16DQ14DQ12VSSDQ10DQ8DQ6VDD3DQ4DQ2DQ0VSSPRESENCE DETECT TABLECache Size andFunctionality256K Pipe Burst512K Pipe BurstPD0NCVSSPD1NCVSSPD2VSSNCPD3NCVSSMCMPC32T•MCMPCT4MOTOROLA FAST SRAM元器件交易网www.cecb2b.comPIN DESCRIPTIONS160–Lead Card Edge Pin Locations20, 21, 22, 23, 24, 26, 28, 29,101, 102, 103, 104, 106, 108, 109, 11030SymbolA3 – A18ADSPTypeInputInputDescriptionAddress Inputs: These inputs are registered into data RAMs and mustmeet setup and hold times. The tag RAM addresses are not registered.Address Status Processor: Initiates READ, WRITE, or chip deselectcycle (Exception–chip deselect does not occur when ADSP is assertedand CCS is high.Burst Order Select: NC for interleaved burst counter. Tie to ground forlinear burst counter.Byte Write Enable: To be used in future modules.Cache Address Status: Initiates READ, WRITE, or chip deselect cycle.Cache Burst Advance: Increments address count in accordance withinterleaved count style.Chip Select: Active low chip enable for data RAMs.Cache Output Enable: Active low asynchronous input.Low–enables output buffers (DQ pins)High–DQx pins are high impedance.Clock: This signal registers the address, data in, and all control signalsexcept CG.Cache Data Byte Write Enable: Active low write signal for data RAMs.Synchronous Data I/O:Drives data out of data RAMs during READ cycles.Stores data to data RAMs during WRITE cycles.11411691BOSELBWECADSCADVCCSCGInputInputInputInputInputInput36, 11611, 12, 13, 14, 92, 93, 94, 9638, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51,53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66,67, 69, 70, 71, 73, 74, 75, 77, 78, 79,118, 120, 121, 122, 124, 125, 126, 127,129, 130, 131, 133, 134, 135, 137, 138,139, 141, 142, 143, 145, 146, 147, 149,150, 151, 153, 154, 155, 157, 158, 15931, 321733, 34, 112, 113100, 1112, 3, 4, 5, 82, 83, 84, 85CLK0,CLK1CWE0 –CWE7DQ0 –DQ63InputInputI/OECS1,ECS2GWEPD0 –PD3RSVDTIO0 –TIO7TWEVDD3VDD5VSSInputInput——I/OExpansion Chip SelectGlobal Write Enable: To be used in future modules.Presence Detect: See Presence Detect TableNo Connection: Reserved for future use.Tag RAM I/O:Drives data out during tag compare cycles.Stores data to tag RAM during tag WRITE cycles.Tag Write Enable: Active low write signal for tag RAMs.Power Supply: 3.3 V + 10%, –5%.Power Supply: 5.0 V ±5%.Ground87, 15, 25, 39, 52, 60, 68, 7687, 95, 105, 119, 132, 140, 148, 1561, 10, 19, 27, 35, 37, 43, 48, 56, , 72,80, 81, 90, 99, 107, 115, 117, 123, 128,136, 144, 152, 1606, 86, 88, 97, 98InputSupplySupplySupplyNC—No Connection: There is no connection to the module.MOTOROLA FAST SRAMMCMPC32T•MCMPCT5元器件交易网www.cecb2b.comSYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)CCSHLLLXXXXHHHHADSPXLHHHHHHXXXXCADSLXLLHHHHHHHHCADVXXXXLLHHLLHHCWExXXLHLHLHLHLHCLK0L–HL–HL–HL–HL–HL–HL–HL–HL–HL–HL–HL–HAddress UsedN/AExternal AddressExternal AddressExternal AddressNext AddressNext AddressCurrent AddressCurrent AddressNext AddressNext AddressCurrent AddressCurrent AddressOperationDeselectedRead Cycle, Begin BurstWrite Cycle, Begin BurstRead Cycle, Begin BurstWrite Cycle, Continue BurstRead Cycle, Continue BurstWrite Cycle, Suspend BurstRead Cycle, Suspend BurstWrite Cycle, Continue BurstRead Cycle, Continue BurstWrite Cycle, Suspend BurstRead Cycle, Suspend BurstNOTES:1.X means Don’t Care.2.All inputs except CG must meet setup and hold times for the low–to–high transition of clock (CLK0/1).3.Wait states are inserted by suspending burst.ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)OperationReadReadWriteDeselectedCGLHXXI/O StatusData OutHigh–ZHigh–Z — Data InHigh–ZNOTES:1.X means Don’t Care.2.For a write operation following a read operation, G must be high before the input datarequired setup time and held high through the input data hold time.DC ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)RatingPower Supply VoltageVoltage Relative to VSSOutput Current (per I/O)Temperature Under BiasOperating TemperatureStorage TemperatureSymbolVDD3Vin, VoutIoutTbiasTJValue– 0.5 to + 4.6VSS – 0.5 to VDD3 + 0.5± 20– 10 to + 8520 to +110UnitVVmA°C°CTstg– 55 to + 125°CNOTE:Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS areexceeded. Functional operation should be restricted to RECOMMENDED OPER-ATING CONDITIONS. Exposure to higher than recommended voltages forextended periods of time could affect device reliability.This device contains circuitry to protect theinputs against damage due to high static volt-ages or electric fields; however, it is advisedthat normal precautions be taken to avoidapplication of any voltage higher than maxi-mum rated voltages to this high–impedancecircuit.This BiCMOS memory circuit has beendesigned to meet the dc and ac specificationsshown in the tables, after thermal equilibriumhas been established.This device contains circuitry that willensure the output devices are in High–Z atpower up.MCMPC32T•MCMPCT6MOTOROLA FAST SRAM元器件交易网www.cecb2b.comDC OPERATING CONDITIONS AND CHARACTERISTICS(VDD = 3.3 V + 10%, –5%, TJ = 20 to + 110°C, Unless Otherwise Noted)RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)ParameterSupply Voltage (Operating Voltage Range)Input High VoltageInput Low VoltageSymbolVDDVIHVILMin3.1352.0– 0.5Max3.6VDD + 0.30.8UnitVVVNotes123NOTES:1.JEDEC specification 8–1A specifies ± 0.3 V tolerance for VDD.2.VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 1.4 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.3.VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.DC CHARACTERISTICSParameterInput Leakage Current (All Inputs, Vin = 0 to VDD3)Output Leakage Current (CG = VIH)TTL Output Low Voltage (IOL = + 8.0 mA)TTL Output High Voltage (IOH = – 4.0 mA)NOTES:1.Champing diodes exist to VSS and VDD.SymbolIlkg(I)Ilkg(O)VOLVOHMin———2.4Max±1.0±1.00.4—UnitµAµAVV11NotesPOWER SUPPLY CURRENTSParameterAC Supply Current (CG = VIH, CCS = VIL, Iout = 0 mA, All Inputs = VIL or VIH,VIL = 0.0 V and VIH ≥3.0 V, Cycle Time ≥ tKHKH min)AC Standby Current (CG = VIH, CCS = VIL, Iout = 0 mA, All Inputs = VIL or VIH,VIL = 0.0 V and VIH ≥3.0 V, Cycle Time ≥ tKHKH min)MCMPC32TMCMPCTMCMPC32TMCMPCTSymbolIDDAISB1Max495705230505UnitmAmACAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TJ = 20 to 110°C, Periodically Sampled Rather Than 100% Tested)ParameterInput CapacitanceInput/Output Capacitance (DQ0 – DQ63)MCMPC32TMCMPCTMCMPC32TMCMPCTSymbolCinCI/OMax2131816UnitpFpFMOTOROLA FAST SRAMMCMPC32T•MCMPCT7元器件交易网www.cecb2b.comDATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS(VDD = 3.3 V + 10%, –5% TJ = 20 to + 110°C, Unless Otherwise Noted)Input Timing Measurement Reference Level. . . . . . . . . . . . . . . 1.5 VInput Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 VInput Rise/Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 nsOutput Timing Reference Level. . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 VOutput Load. . . . . . . . . . . . . . See Figure 3 Unless Otherwise NotedOUTPUT LOADOUTPUTBUFFERTEST POINT(UNLOADED OUTPUT)UNLOADED RISE AND FALL TIME MEASUREMENTINPUTWAVEFORM2.4OUTPUTWAVEFORM0.4trNOTES:1.Input waveform should have a slew rate of 1 V/ns.2.Rise time is measure from 0.4 V to 2.4 V unloaded.3.Fall time is measure from 2.4 V to 0.4 V unloaded.tf2.40.4Figure 1. Unloaded Rise and Fall time CharacterizationMCMPC32T•MCMPCT8MOTOROLA FAST SRAM元器件交易网www.cecb2b.comDATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)MCMPC32T–66MCMPC32T–66ParameterCycle TimeClock Access TimeOutput Enable to Output ValidClock High to Output ActiveClock High to Output ChangeOutput Enable to Output ActiveOutput Disable to Q High–ZClock High to Q High–ZClock High Pulse WidthClock Low Pulse WidthSetup Times:AddressAddress StatusData InWriteAddress AdvanceChip EnableAddressAddress StatusData InWriteAddress AdvanceChip EnableSymboltKHKHtKHQVtGLQVtKHQX1tKHQX2tGLQXtGHQZtKHQZtKHKLtKLKHtAVKHtADSVKHtDVKHtWVKHtADVVKHtEVKHtKHAXtKHADSXtKHDXtKHWXtKHADVXtKHEXMin15——020—2552.5Max—86———88———Unitnsnsnsnsnsnsnsnsnsnsns4555, 75, 75, 76, 76, 7NotesHold Times:0.5—ns4NOTES:1.Write applies to all SBx, SW, and SGW signals when the chip is selected and ADSP high.2.Chip Enable applies to all SE1, SE2 and SE3 signals whenever ADSP or ADSC is asserted.3.All read and write cycle timings are referenced from K or G.4.G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.5.Tested per AC Test Load.6.Measured at ± 200 mV from steady state. Tested per High–Z Test Load.7.This parameter is sampled and is not 100% tested.MOTOROLA FAST SRAMMCMPC32T•MCMPCT9元器件交易网www.cecb2b.comPULL–UPVOLTAGE (V)– 0.501.41.6523.1353.6I (mA) Min– 40– 40– 40– 37– 2800I (mA) Max– 120– 120– 120– 104– 81– 200AC DRIVEPOINT00– 5– 40– 80– 120NOTES:CURRENT (mA)1.Driver impedance @ 1.65 V = 15.9 to 44.6 Ω.2.Meets the temperature and voltage range specified in DC Characteristics tables.3.This drawing is not to scale. Comparisons should be made to the table in Figure 2a.VOLTAGE (V)DC DRIVEPOINT1.651.43.1352.8TEST POINT3.62a. Pull–UpPULL–DOWNVOLTAGE (V)– 0.500.511.651.83.I (mA) Min– 34017354546I (mA) Max– 12604790114120120120VOLTAGE (V)VDDAC DRIVEPOINT1.81.65DC DRIVEPOINT0.30054680CURRENT (mA)120TEST POINTNOTES:1.Driver impedance @ 1.65 V = 15.9 to 44.6 Ω.2.Meets the temperature and voltage range specified in DC Characteristics tables.3.This drawing is not to scale. Comparisons should be made to the table in Figure 2b.2b. Pull–DownFigure 2. Output Buffer CharacteristicsMCMPC32T•MCMPCT10MOTOROLA FAST SRAMDATA RAMs READ/WRITE CYCLEStKHKHtKHKLtKLKHCLK0, CLK1元器件交易网www.cecb2b.comMOTOROLA FAST SRAMBCDtKHQVBURST WRAPS AROUNDQ(A)tKHQX1tKHQX2Q(B)Q(B+1)Q(B+2)Q(B+3)Q(B)tGHQZD(C)ADSP, AxESC1 IGNOREDBURST READBURST WRITED(C+1)D(C+2)D(C+3)tGLQXQ(D)SINGLE READSINGLE READAx (ADDRESS)AADSPCADSCADVCCSESC1WtKLQZCGtKHQZtKHQVDQxQ(n–1)DESELECTEDMCMPC32T•MCMPCT11Note: W low = GWE low and/or BWE and CWEx low.元器件交易网www.cecb2b.comTAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS(VDD = 3.3 V ± 0.3 V, TJ = 20 to +110°C, Unless Otherwise Noted)Input Timing Measurement Reference Level. . . . . . . . . . . . . . . 1.5 VInput Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 VInput Rise/Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 nsOutput Timing Measurement Reference Level. . . . . . . . . . . . . 1.5 VOutput Load. . . . . . . . . . . . . . . . . . Figure 3 Unless Otherwise NotedTAG RAM READ CYCLE (See Notes 1 and 2)–15ParameterRead Cycle TimeAddress Access TimeOutput Hold from Address ChangeSymboltAVAVtAVQVtAXQXMin15—4Max—15—Unitnsnsns4, 5Notes3NOTES:1.CWE is high for read cycle.2.Device is continuously selected (CG = VIL).3.All timings are referenced from the last valid address to the first address transition.4.Transition is measured ±500 mV from steady–state voltage with load of Figure 3b.5.This parameter is sampled and not 100% tested.TAG RAM READ CYCLE (See Note 5)tAVAVAx (ADDRESS)tAXQXQ (DATA OUT)PREVIOUS DATA VALIDtAVQVDATA VALID3.3 VZ0 = 50 ΩOUTPUT50 ΩVL = 1.5 VOUTPUT351 Ω5 pF317 ΩTIMING LIMITSThe table of timing values shows either aminimum or a maximum limit for each param-eter. Input requirements are specified fromthe external system point of view. Thus, ad-dress setup time is shown as a minimumsince the system must supply at least thatmuch time. On the other hand, responsesfrom the memory are specified from the de-vice point of view. Thus, the access time isshown as a maximum since the device neverprovides data later than that time.(a)(b)Figure 3. Test LoadsMCMPC32T•MCMPCT12MOTOROLA FAST SRAM元器件交易网www.cecb2b.comTAG RAM WRITE CYCLE (See Notes 1 and 2)–15ParameterWrite Cycle TimeAddress Setup TimeAddress Valid to End of WriteData Valid to End of WriteData Hold TimeWrite Low to Output High–ZWrite High to Output ActiveWrite Recovery TimeSymboltAVAVtAVWLtAVWHtDVWHtWHDXtWLQZtWHQXtWHAXMin1501270040Max—————7——Unitnsnsnsnsnsnsnsns5,6,75,6,7Notes3NOTES:1.A write occurs when CWE is low.2.If CG goes low coincident with or after CWE goes low, the output will remain in a high impedance state.3.All timings are referenced from the last valid address to the first address transition.4.If CG ≥ VIH, the output will remain in a high impedance state.5.At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.6.Transition is measured ±500 mV from steady–state voltage with load of Figure 3b.7.This parameter is sampled and not 100% tested.TAG RAM WRITE CYCLE (See Notes 1 and 2)tAVAVAX (ADDRESS)tAVWHtWLWHTWEtAVWLD (DATA IN)tWLQZQ (DATA OUT)HIGH ZHIGH ZtDVWH DATA VALIDtWHQXtWHDXtWHAXMOTOROLA FAST SRAMMCMPC32T•MCMPCT13元器件交易网www.cecb2b.comORDERING INFORMATION(Order by Full Part Number)PC32TPCTXXMCMMotorola Memory PrefixPart NumberXXSpeed (66 = 66 MHz)Package (SG = Gold Pad SIMM)Full Part Number —MCMPC32TSG66MCMPCTSG66MCMPC32T•MCMPCT14MOTOROLA FAST SRAM元器件交易网www.cecb2b.comPACKAGE DIMENSIONS160–LEADCARD EDGE MODULECASE TBDAECOMPONENTAREACNOTE 4B804342MIN .285 inches,MAX .305 inches1PVNOTE 4–Y–VIEWAAL2XFAC–X–MABNOTE 5J–T–SIDE VIEWNOTE 6FRONT VIEW0.012 (0.3)M160XD0.004 (0.1)LTYXSR160XH160XKRW(N)156XGNOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.CARD THICKNESS APPLIES ACROSS TABS ANDINCLUDES PLATING AND/OR METALLIZATION.4.DIMENSIONS C AND V DEFINE ADOUBLE–SIDED MODULE.5.DIMENSION AB DEFINES OPTIONALSINGLE–SIDED MODULE.6.STRAIGHTNESS CALLOUT APPLIES TO TABAREA ONLY.DIMABCDEFGHJKLMNPRVWABACINCHESMINMAX4.3304.3501.1201.140–––0.4540.0330.0372.2652.2750.075 BSC0.050 BSC–––0.0300.0550.0690.210–––1.9551.9652.1552.1650.110 REF0.300–––0.4920.5120.300–––0.0400.060–––0.2620.0720.076MILLIMETERSMINMAX109.98110.4928.4528.96–––11.530.840.9457.5357.791.91 BSC1.27 BSC–––0.511.401.755.33–––49.69.9154.7454.992.79 REF7.62–––7.247.757.62–––1.021.52–––6.661.831.93VIEW AA16012312281COMPONENTAREABACK VIEWNOTE: Case Outline number to be determined.MOTOROLA FAST SRAMMCMPC32T•MCMPCT15元器件交易网www.cecb2b.comMotorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motoroladata sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights ofothers. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or otherapplications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injuryor death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorolaand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatMotorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an EqualOpportunity/Affirmative Action Employer.Mfax is a trademark of Motorola, Inc.How to reach us:USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;P.O. Box 5405, Denver, Colorado, 80217.303–675–2140 or 1–800–441–2447Mfax™: RMFAX0@email.sps.mot.com — TOUCHTONE 602–244–6609INTERNET: http://Design–NET.comJAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298MCMPC32T•MCMPCT◊16MCMPC32T/DMOTOROLA FAST SRAM
