元器件交易网www.cecb2b.com 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGTLV5625CONVERTER WITH POWER DOWNSLAS233A – JULY 1999 – REVISED MARCH 2000featuresapplicationsDDual 8-Bit Voltage Output DACDDDigital Servo Control LoopsProgrammable Internal ReferenceDDDigital Offset and Gain AdjustmentProgrammable Settling Time– 2.5 µs in Fast ModeDIndustrial Process Control– 12 µs in Slow ModeDMachine and Motion Control DevicesDCompatible With TMS320 and SPI™ SerialDMass Storage DevicesPortsDDifferential Nonlinearity <0.2 LSB MaxD PACKAGE(TOP VIEW) DMonotonic Over TemperatureDIN18VdescriptionDDSCLK27OUTBThe TLV5625 is a dual 8-bit voltage output DACCS36REFwith a flexible 3-wire serial interface. The serialOUTA45AGNDinterface is compatible with TMS320, SPI™,QSPI™, and Microwire™ serial ports. It isprogrammed with a 16-bit serial string containing4 control and 8 data bits.The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features aClass-AB output stage to improve stability and reduce settling time. The programmable settling time of the DACallows the designer to optimize speed versus power dissipation.Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. Itis available in an 8-pin SOIC package in standard commercial and industrial temperature ranges.AVAILABLE OPTIONSPACKAGETASOIC(D)0°C to 70°CTLV5625CD–40°C to 85°CTLV5625IDPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SPI and QSPI are trademarks of Motorola, Inc.Microwire is a trademark of National Semiconductor Corporation.PRODUCT PREVIEW information concerns products in the formative orCopyright © 2000, Texas Instruments Incorporateddesign phase of development. Characteristic data and otherspecifications are design goals. Texas Instruments reserves the right tochange or discontinue these products without notice.POST OFFICE BOX 655303 • DALLAS, TEXAS 752651PRODUCT PREVIEW元器件交易网www.cecb2b.comSLAS233A – JULY 1999 – REVISED MARCH 2000TLV56252.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGCONVERTER WITH POWER DOWNfunctional block diagramREFAGNDVDD Power-OnResetPower andSpeed Control2x2DIN8SCLKSerialInterfaceandControl8-BitDAC ALatch8OUTAPRODUCT PREVIEW8Buffer88-BitDAC BLatch8x2CSOUTBTerminal FunctionsTERMINALNAMEAGNDCSDINOUTAOUTBREFSCLKVDDNO.53147628I/O/PPIIOOIIPGroundChip select. Digital input active low, used to enable/disable inputs.Digital serial data inputDAC A analog voltage outputDAC B analog voltage outputAnalog reference voltage inputDigital serial clock inputPositive power supplyDESCRIPTION2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV56252.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGCONVERTER WITH POWER DOWNSLAS233A – JULY 1999 – REVISED MARCH 2000absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VReference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 VDigital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 VOperating free-air temperature range, TA:TLV5625C 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 70°CTLV5625I –40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 85°CStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.recommended operating conditionsMINSupplyvoltageVDDSupply voltage, VPower on reset, PORHigh-level digital input voltage, VIHLow-level digital input voltage, VILReference voltage, Vref to REF terminalReference voltage, Vref to REF terminalLoad resistance, RLLoad capacitance, CLClock frequency, fCLKOperating free-air temperature, TOperatingfreeairtemperatureTATLV5625CTLV5625I0–40VDD = 2.7 V to 5.5 VVDD = 2.7 V to 5.5 VVDD = 5 V (see Note 1)VDD = 3 V (see Note 1)VDD = 5 VVDD = 3 V4.52.70.5520.8AGNDAGND21002070852.0481.024VDD–1.5VDD–1.5NOM53MAX5.53.32VVVVkΩpFMHz°CVUNITVNOTE 1:Due to the x2 output buffer, a reference input voltage ≥ (VDD–0.4 V)/2 causes clipping of the transfer function.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3PRODUCT PREVIEW元器件交易网www.cecb2b.comSLAS233A – JULY 1999 – REVISED MARCH 2000TLV56252.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGCONVERTER WITH POWER DOWNelectrical characteristics over recommended operating conditions (unless otherwise noted)power supplyPARAMETERIDDPowersupplyycurrentPower suly currentPower-down supply currentPSRRPowersupplyrejectionratioPower supply rejection ratioZero scale, See Note 2Full scale, See Note 3TEST CONDITIONSNo load, All inputs = AGND or VDD,DAC latch = 0x800DAClatch0x800FastSlowMINTYP1.80.81–65–65MAX2.313UNITmAµAdB NOTES:2.Power supply rejection ratio at zero scale is measured by varying VDD and is given by:PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin)/VDDmax]3.Power supply rejection ratio at full scale is measured by varying VDD and is given by:PSRR = 20 log [(EG(VDDmax) – EG(VDDmin)/VDDmax]static DAC specificationsPARAMETERResolutionINLIntegral nonlinearityDifferential nonlinearityZero-scale error (offset error at zero scale)Zero-scale-error temperature coefficientGain errorGain-error temperature coefficientSee Note 4See Note 5See Note 6See Note 7See Note 8See Note 91010±0.5DNLEZSEZS TCEGEG TCTEST CONDITIONSMIN8±0.3±0.07±0.5±0.2±12TYPMAXUNITbitsLSBLSBmVppm/°C% fullscale Vppm/°CPRODUCT PREVIEWNOTES:4.The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the outputfrom the line between zero and full scale, excluding the effects of zero-code and full-scale errors.5.The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal1-LSB amplitude change of any two adjacent codes.6.Zero-scale error is the deviation from zero voltage output when the digital input code is zero.7.Zero-scale error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/2Vref ×106/(Tmax – Tmin).8.Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 kΩ.9.Gain temperature coefficient is given by: EG TC = [EG (Tmax) – Eg (Tmin)]/2Vref ×106/(Tmax – Tmin).output specificationsPARAMETERVOOutput voltage rangeOutput load regulation accuracyTEST CONDITIONSRL = 10 kΩVO = 4.096 V, 2.048 V RL = 2 kΩMIN0TYPMAXVDD–0.4±0.29UNITV% FSreference inputPARAMETERVIRICIInput voltage rangeInput resistanceInput capacitanceReferenceinputbandwidthReference input bandwidthReference feedthroughREF=02Vpp + 1.024 V dc+1024VdcREF = 0.2 VREF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)FastSlowTEST CONDITIONSMIN01051.3525–80TYPMAXVDD–1.5UNITVMΩpFMHzkHzdBNOTE 10:Reference feedthrough is measured at the DAC output with an input code = 0x000.4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV56252.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGCONVERTER WITH POWER DOWNSLAS233A – JULY 1999 – REVISED MARCH 2000electrical characteristics over recommended operating conditions (unless otherwise noted)(Continued)digital inputsPARAMETERIIHIILCiHigh-level digital input currentLow-level digital input currentInput capacitanceTEST CONDITIONSVI = VDDVI = 0 VMIN–18TYPMAX1UNITµAµApFanalog output dynamic performancePARAMETERts(FS)(FS)ts(CC)(CC)SROutputsettlingtimefullscaleOutput settling time, full scaleOutputsettlingtimecodetocodeOutput settling time, code to codeSlewrateSlew rateGlitch energySNRSINADTHDSFDRSignal-to-noise ratioSignal-to-noise + distortionTotal harmonic distortionSpurious free dynamic rangefs = 102 kSPS,,fout = 1 kHz,,RL = 10 kΩ,CL = 100 pFTEST CONDITIONSRL = 10 kΩ,See Note 11RL = 10 kΩ,See Note 12RL = 10 kΩ,See Note 13DIN = 0 to 1,CS = VDDCL = 100 pF,,CL = 100 pF,,CL = 100 pF,,FastSlowFastSlowFastSlowFCLK = 100 kHz,524848MINTYP2.5121230.555449–5050–48dBMAXUNITµsµsV/µsnV–sNOTES:11.Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code changeof 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.12.Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code changeof one count. Not tested, assured by design.13.Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•5PRODUCT PREVIEW元器件交易网www.cecb2b.comSLAS233A – JULY 1999 – REVISED MARCH 2000TLV56252.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGCONVERTER WITH POWER DOWNdigital input timing requirementsMINtsu(CS–CK)tsu(C16-CS)twHtwLtsu(D)th(D)Setup time, CS low before first negative SCLK edgeSetup time, 16th negative SCLK edge before CS rising edgeSCLK pulse width highSCLK pulse width lowSetup time, data ready before SCLK falling edgeHold time, data held valid after SCLK falling edge10102525105NOMMAXUNITnsnsnsnsnsns timing requirementstwLtwHSCLKX1tsu(D)th(D)23451516XPRODUCT PREVIEWDINXD15D14D13D12D1D0Xtsu(C16-CS)tsu(CS-CK)CSFigure 1. Timing Diagram6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV56252.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGCONVERTER WITH POWER DOWNSLAS233A – JULY 1999 – REVISED MARCH 2000TYPICAL CHARACTERISTICS2.0502.048VO– Output Voltage – V2.0462.0442.0422.0402.0382.036OUTPUT VOLTAGEvsLOAD CURRENT3 V Slow Mode, SOURCEVDD=3 VVREF=1 VFull scaleVO– Output Voltage – V4.1054.1004.0954.0904.0854.0804.0754.070OUTPUT VOLTAGEvsLOAD CURRENT5 V Slow Mode, SOURCEVDD=5 VVREF=2 VFull scale3 V Fast Mode, SOURCE5 V Fast Mode, SOURCE0.00–0.01–0.02–0.05–0.10–0.20–0.51–1.02–2.05Load Current - mA0.00–0.02–0.04–0.10–0.20–0.41–1.02–2.05–4.10Load Current - mAFigure 2OUTPUT VOLTAGEvsLOAD CURRENT0.200.180.16VO– Output Voltage – V0.140.120.100.080.060.040.020.000.000.010.020.050.100.200.511.022.05Load Current - mA0.050.003 V Fast Mode, SINKVDD=3 VVREF=1 VZero scaleVO– Output Voltage – V3 V Slow Mode, SINK0.350.300.250.200.15VDD=5 VVREF=2 VZero scaleFigure 3OUTPUT VOLTAGEvsLOAD CURRENT5 V Slow Mode, SINK5 V Fast Mode, SINK0.100.000.020.040.100.200.411.022.054.09Load Current - mAFigure 4Figure 5POST OFFICE BOX 655303 DALLAS, TEXAS 75265•7PRODUCT PREVIEW元器件交易网www.cecb2b.comSLAS233A – JULY 1999 – REVISED MARCH 2000TLV56252.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGCONVERTER WITH POWER DOWNTYPICAL CHARACTERISTICSSUPPLY CURRENTvsFREE-AIR TEMPERATURE1.801.60IDD– Supply Current – mA1.401.201.000.800.600.400.200.00–40.00–20.000.0020.0040.0060.0080.00100.00120.00TA - Free-Air Temperature - CSlow ModeVDD=3 VVREF=1 VFull scale1.801.60Fast ModeIDD– Supply Current – mA1.401.201.000.800.600.400.20Slow ModeVDD=5 VVREF=2 VFull scale SUPPLY CURRENTvsFREE-AIR TEMPERATUREFast ModePRODUCT PREVIEW0.00–40.00–20.000.0020.0040.0060.0080.00100.00120.00TA - Free-Air Temperature - CFigure 6TOTAL HARMONIC DISTORTIONvsFREQUENCY0.00THD - Total Harmonic Distortion - dB–10.00–20.00–30.00–40.00–50.003 V Fast Mode–60.00–70.00–80.00–90.00110f - Frequency - kHz100VREF = 1 V + 1 VP/P Sinewave,Output Full Scale0.00–10.00THD - Total Harmonic Distortion - dB–20.00–30.00–40.00–50.00–60.00–70.00–80.00–90.001Figure 7TOTAL HARMONIC DISTORTIONvsFREQUENCYVREF = 1 V + 1 VP/P Sinewave,Output Full Scale3 V Slow Mode5 V Slow Mode5 V Fast Mode10f - Frequency - kHz100Figure 8Figure 98POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV56252.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGCONVERTER WITH POWER DOWNSLAS233A – JULY 1999 – REVISED MARCH 2000TYPICAL CHARACTERISTICSDIFFERENTIAL NONLINEARITYvsDIGITAL OUTPUT CODEDNL – Differential Nonlinearity – LSB0.100.080.060.040.020.00–0.02–0.04–0.06–0.08–0.100128Digital Output Code192255Figure 10INTEGRAL NONLINEARITYvsDIGITAL OUTPUT CODEINL – Integral Nonlinearity – LSB0.50.40.30.20.1–0.0–0.1–0.2–0.3–0.4–0.50128Digital Output Code192255Figure 11POST OFFICE BOX 655303 DALLAS, TEXAS 75265•9PRODUCT PREVIEW元器件交易网www.cecb2b.comSLAS233A – JULY 1999 – REVISED MARCH 2000TLV56252.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGCONVERTER WITH POWER DOWNAPPLICATION INFORMATIONgeneral function The TLV5625 is a dual 8-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serialinterface, a speed and power-down control logic, a resistor string, and a rail-to-rail output buffer.The output voltage (full scale determined by the reference) is given by:2REFCODE[V]0x1000Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFF0. A power-onreset initially puts the internal latches to a defined state (all bits zero).serial interfaceA falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the fallingedges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to thetarget latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.PRODUCT PREVIEWFigure 2 shows examples of how to connect the TLV5625 to TMS320, SPI™, and Microwire™.TMS320DSPFSXDXCLKXTLV5625CSDINSCLKSPII/OMOSISCKTLV5625CSDINSCLKMicrowireI/OSOSKTLV5625CSDINSCLKFigure 12. Three-Wire InterfaceNotes on SPI™ and Microwire™: Before the controller starts the data transfer, the software has to generate afalling edge on the pin connected to CS. If the word width is 8 bits (SPI™ and Microwire™) two write operationsmust be performed to program the TLV5625. After the write operation(s), the holding registers or the controlregister are updated automatically on the 16th positive clock edge.serial clock frequency and update rateThe maximum serial clock frequency is given by:fsclkmax+1+20MHztwhmin)twlminThe maximum update rate is:fupdatemax+16ǒtwhmin)twlminǓ1+1.25MHzNote that the maximum update rate is just a theoretical value for the serial interface, as the settling time of theTLV5625 should also be considered.10POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGTLV5625CONVERTER WITH POWER DOWNSLAS233A – JULY 1999 – REVISED MARCH 2000APPLICATION INFORMATIONdata formatThe 16-bit data word for the TLV5625 consists of two parts:DProgram bits (D15..D12)DNew data (D11..D4)D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0R1SPDPWRR0MSB8 Data bitsLSB0000SPD: Speed control bit1 → fast mode0 →slow modePWR: Power control bit1 → power down0 → normal operationOn power up, SPD and PWD are reset to 0 (slow mode and normal operation)The following table lists all possible combination of register-select bits:register-select bitsR1R0REGISTER00Write data to DAC B and BUFFER01Write data to BUFFER10Write data to DAC A and update DAC B with BUFFER content11ReservedThe meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,then the 12 data bits determine the new DAC value:examples of operationDSet DAC A output, select fast mode:Write new DAC A value and update DAC A output:D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D01100New DAC A output value0000The DAC A output is updated on the rising clock edge after D0 is sampled.DSet DAC B output, select fast mode:Write new DAC B value to BUFFER and update DAC B output:D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D00100New BUFFER content and DAC B output value0000The DAC A output is updated on the rising clock edge after D0 is sampled.DSet DAC A value, set DAC B value, update both simultaneously, select slow mode:1.Write data for DAC B to BUFFER:D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D00001New DAC B value00002.Write new DAC A value and update DAC A and B simultaneously:D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D01000New DAC A value0000POST OFFICE BOX 655303 • DALLAS, TEXAS 7526511PRODUCT PREVIEW元器件交易网www.cecb2b.comSLAS233A – JULY 1999 – REVISED MARCH 2000TLV56252.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGCONVERTER WITH POWER DOWNAPPLICATION INFORMATIONexamples of operation (continued)Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled. DSet power-down mode:D15XD14XD131D12XD11XD10XD9XD8XD7XD6XD5XD4XD3XD2XD1XD0XX = Don’t carelinearity, offset, and gain error using single ended suppliesWhen an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. Witha positive offset, the output voltage changes on the first code change. With a negative offset, the output voltagemay not change with the first code, depending on the magnitude of the offset voltage.The output amplifier attempts to drive the output to a negative voltage. However, because the most negativesupply rail is ground, the output cannot drive below ground and clamps the output at 0 V.PRODUCT PREVIEWThe output voltage then remains at zero until the input code value produces a sufficient positive output voltageto overcome the negative offset voltage, resulting in the transfer function shown in Figure 13.OutputVoltage0 VNegativeOffsetDAC CodeFigure 13. Effect of Negative Offset (Single Supply)This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed thedotted line if the output buffer could drive below the ground rail.For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) afteroffset and full scale are adjusted out or accounted for in some way. However, single supply operation does notallow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearityis measured between full-scale code and the lowest code that produces a positive output voltage.power-supply bypassing and ground managementPrinted-circuit boards that use separate analog and digital ground planes offer the best system performance.Wire-wrap boards do not perform well and should not be used. The two ground planes should be connectedtogether at the low-impedance power-supply source. The best ground connection may be achieved byconnecting the DAC AGND terminal to the system analog ground plane, making sure that analog groundcurrents are well managed and there are negligible voltage drops across the ground plane.A 0.1-µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leadsas close as possible to the device. Use of ferrite beads may further isolate the system analog supply from thedigital power supply.Figure 14 shows the ground plane layout and bypassing technique.12POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV56252.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGCONVERTER WITH POWER DOWNSLAS233A – JULY 1999 – REVISED MARCH 2000APPLICATION INFORMATIONAnalog Ground Plane123487650.1 µFFigure 14. Power-Supply Bypassingdefinitions of specifications and terminologyintegral nonlinearity (INL)The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximumdeviation of the output from the line between zero and full scale excluding the effects of zero code and full-scaleerrors.differential nonlinearity (DNL)The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between themeasured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltagechanges in the same direction (or remains constant) as a change in the digital input code.zero-scale error (EZS)Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.gain error (EG)Gain error is the error in slope of the DAC transfer function.signal-to-noise ratio + distortion (S/N+D)S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components belowthe Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.spurious free dynamic range (SFDR)SFDR is the difference between the rms value of the output signal and the rms value of the largest spurioussignal within a specified bandwidth. The value for SFDR is expressed in decibels.total harmonic distortion (THD)THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signaland is expressed in decibels.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•13PRODUCT PREVIEW元器件交易网www.cecb2b.comSLAS233A – JULY 1999 – REVISED MARCH 2000TLV56252.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOGCONVERTER WITH POWER DOWNMECHANICAL DATAD (R-PDSO-G**) 14 PIN SHOWN PLASTIC SMALL-OUTLINE PACKAGE0.050 (1,27)0.020 (0,51)0.014 (0,35)1480.008 (0,20) NOM0.244 (6,20)0.228 (5,80)0.157 (4,00)0.150 (3,81)0.010 (0,25)MGage Plane0.010 (0,25)PRODUCT PREVIEW1A70°–8°0.044 (1,12)0.016 (0,40)Seating Plane0.069 (1,75) MAX0.010 (0,25)0.004 (0,10)0.004 (0,10)PINS **DIMA MAX80.197(5,00)0.1(4,80)140.344(8,75)0.337(8,55)160.394(10,00)0.386(9,80)4040047/D 10/96A MINNOTES:A.B.C.D.All linear dimensions are in inches (millimeters).This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).Falls within JEDEC MS-01214POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com
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