CompactFlash Card Interface for CoolRunner-II CPLDs
Table 2: Common Memory Interface Pin Descriptions
Name
cm_sts
DirectionInput
Description
Effectively a ready/busy signal for the Intel StrataFlash. This implementation assumes the memory is configured with level mode sts
signalling and therefore supplies the CF+ rdy/-bsy logic (named ireq_n) a busy state (LOW) when the memory is busy performing a lengthy operation. cm_sts is active LOW.
Available for Common Memory wait type status inputs. As the Intel StrataFlash memory used in this implementation does not contain a wait signal, cm_wait is unused and driven high in the test bench. The user must either permanently drive this signal HIGH or remove it from the source code so as to allow proper functionality of wait_n. cm_wait is active LOW.
Active LOW, cm_byte_n selects the 8-bit or 16-bit data bus access modes of the Intel StrataFlash as requested by the HBA. When in 8-bit mode, cm_addr(0) selects the high or low byte of the addressed memory location. When in 16-bit mode, cm_addr(0) is ignored and cm_addr(1) becomes the LSB of the Common Memory address bus.Byte-select address for the Intel StrataFlash. This signal selects the high or low byte of the
addressed memory location. A high byte from Common Memory corresponds to an odd byte with respect to the CF+ interface. Similarly, a low byte from Common Memory corresponds to an even byte on the CF+ interface. High bytes are
accessed when cm_addr(0) is HIGH and low bytes are accessed when cm_addr(0) is LOW.Address bus for the Common Memory.Active LOW reset for the Common MemoryActive LOW output enable signal to read data from the Common Memory.
Data bus for the Common Memory.
Active LOW chip enable signal for the Common Memory.
Active LOW write enable signal for the Common Memory.
cm_waitInput
cm_byte_nOutput
cm_addr(0)Output
cm_addr(10:1)cm_resetcm_read_ncm_data(15:0)cm_ce_ncm_write_n
OutputOutputBidirectionalBidirectionalBidirectionalBidirectional
XAPP398 (v1.0) September 23, 2003
CoolRunner-II Serial Peripheral Interface Master
Table 1: CoolRunner-II SPI Master Signal DescriptionWR_NINT_N
InputOutput
Write Strobe. Active Low μC control signal
indicating that the current bus cycle is a write cycle.Interrupt Request. Active Low signal to generate an interrupt to the μC. This signal is asserted when interrupts are enabled and there is SPI bus
contention as indicated by SS_IN_N or when the transmit register is empty (SPITR) during a
transaction, or when the receive register is full and the transaction is complete.
Transmit Register Empty. Active High signal
indicating that the transmit register (SPITR) is empty. This bit is used to signal the loading of data from the SPITR to the SPI transmit shift register indicating that the μC can load another byte of data into the SPITR. This signal could be connected to an μC interrupt or to an I/O port. This signal causes INT_N to assert during data transfers but does not cause an interrupt after the transfer is complete (i.e. START = 0). This signal is brought out of the CPLD as a
separate I/O pin for systems that do not want to use interrupts.
Receive Register Full. Active High signal indicating that the receive register (SPIRR) is full. This bit is used to signal the loading of data from the SPI
receive shift register to the SPIRR. This signal could be connected to an μC interrupt or to an I/O port. This signal causes INT_N to assert only for the last word received from the transfer (i.e., START = 0). This signal is brought out of the CPLD as a separate I/O pin for systems that do not want to use interrupts.Clock. This clock is input from the system and is used to generate the SCK signal.
Reset. Active High reset from the system. When asserted, all logic in the CoolRunner-II CPLD is reset.
XMIT_EMPTYOutput
RCV_FULLOutput
CLKRESET
InputInput
XAPP386 (v1.0) December 12, 2002
