Philips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMDESCRIPTIONFEATURESThe Philips 80C51/87C51/80C52/87C52 is a high-performancestatic 80C51 design fabricated with Philips high-density CMOS•8051 Central Processing Unittechnology with operation from 2.7 V to 5.5 V.–4k × 8 ROM (80C51)The 8xC51 and 8xC52 contain a 128 × 8 RAM and 256 ×8 RAM–8k × 8 ROM (80C52)respectively, 32 I/O lines, three 16-bit counter/timers, a six-source,–128 × 8 RAM (80C51)four-priority level nested interrupt structure, a serial I/O port for–256 × 8 RAM (80C52)either multi-processor communications, I/O expansion or full duplex–Three 16-bit counter/timersUART, and on-chip oscillator and clock circuits.–Boolean processorIn addition, the device is a low power static design which offers a–Full static operationwide range of operating frequencies down to zero. Two softwareselectable modes of power reduction—idle mode and power-down–Low voltage (2.7 V to 5.5 V@ 16 MHz) operationmode are available. The idle mode freezes the CPU while allowing•Memory addressing capabilitythe RAM, timers, serial port, and interrupt system to continue–k ROM and k RAMfunctioning. The power-down mode saves the RAM contents butfreezes the oscillator, causing all other chip functions to be•Power control modes:inoperative. Since the design is static, the clock can be stopped–Clock can be stopped and resumedwithout loss of user data and then the execution resumed from the–Idle modepoint the clock was stopped.–Power-down modeSELECTION TABLE•CMOS and TTL compatibleFor applications requiring more ROM and RAM, see the 8XC54/58•TWO speed ranges at VCC = 5 Vand 8XC51RA+/RB+/RC+/80C51RA+ data sheet.–0 to 16 MHzNote: 80C31/80C32 is specified in separate data sheet.–0 to 33 MHz•Three package stylesROM/EPROMRAM SizeProgrammableHardwareMemory Size(X by 8)Timer CounterWatch Dog•Extended temperature ranges(X by 8)(PCA)Timer•Dual Data Pointers80C31*/80C51/87C51•Security bits:0K/4K128NoNo–ROM (2 bits)80C32*/80C52/87C52–OTP/EPROM (3 bits)0K/8K/16K/32K256NoNo•Encryption array – bytes80C51RA+/8XC51RA+/RB+/RC+•4 level priority interrupt0K/8K/16K/32K512YesYes•6 interrupt sources8XC51RD+•Four 8-bit I/O portsK1024YesYes•Full–duplex enhanced UART–Framing error detection–Automatic address recognition•Programmable clock out•Asynchronous port reset•Low EMI (inhibit ALE and slew rate controlled outputs)•Wake-up from Power Down by an external interruptPrinted from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 2853–0169 24291This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAM80C51/87C51 ORDERING INFORMATIONMEMORY SIZETEMPERATURE RANGE °CVOLTAGEFREQ.4K × 8AND PACKAGERANGE(MHz)DWG. #ROMP80C51SBPNOTPP87C51SBPN00 to +70, Plastic Dual In-line Packageto+70PlasticDualInlinePackage22.7 V to 5.5 V7Vto55V00 to 16to16SOT129SOT129-11ROMP80C51SBAAOTPP87C51SBAA00 to +70, Plastic Leaded Chip Carrierto+70PlasticLeadedChipCarrier22.7 V to 5.5 V7Vto55V00 to 16to16SOT187SOT187-22ROMP80C51SBBBOTPP87C51SBBB00 to +70, Plastic Quad Flat Packto+70PlasticQuadFlatPack22.7 V to 5.5 V7Vto55V00 to 16to16SOT307SOT307-22ROMP80C51SFPNOTPP87C51SFPN–40 to +85, Plastic Dual In-line Package40to+85PlasticDualInlinePackage22.7 V to 5.5 V7Vto55V00 to 16to16SOT129SOT129-11ROMP80C51SFAAOTPP87C51SFAA–40 to +85, Plastic Leaded Chip Carrier40to+85PlasticLeadedChipCarrier22.7 V to 5.5 V7Vto55V00 to 16to16SOT187SOT187-22ROMP80C51SFBBOTPP87C51SFBB–40 to +85, Plastic Quad Flat Pack40to+85PlasticQuadFlatPack22.7 V to 5.5 V7Vto55V00 to 16to16SOT307SOT307-22ROMP80C51UBAAOTPP87C51UBAA00 to +70, Plastic Leaded Chip Carrierto+70PlasticLeadedChipCarrier55 VV00 to 33to33SOT187SOT187-22ROMP80C51UBPNOTPP87C51UBPN00 to +70, Plastic Dual In-line Packageto+70PlasticDualInlinePackage55 VV00 to 33to33SOT129SOT129-11ROMP80C51UFAAOTPP87C51UFAA–40 to +85, Plastic Leaded Chip Carrier40to+85PlasticLeadedChipCarrier55 VV00 to 33to33SOT187SOT187-22PART NUMBER DERIVATIONDEVICEDEVICEOPERATING FREQUENCY, MAX (S)TEMPERATURE RANGE (B)PACKAGE (AA)NUMBERNUMBERROMP80C51S = 16 MHzB = 0_ to +70_CAA = PLCCROMP80C52S = 16 MHzB = 0_ to +70_CAA = PLCCOTPP87C51U = 33 MHzF = –40_C to +85_CBB = PQFPOTPP87C52U = 33 MHzF = –40_C to +85_CBB = PQFPPrinted from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 3This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAM80C52/87C52 ORDERING INFORMATIONMEMORY SIZETEMPERATURE RANGE °CVOLTAGEFREQ.8K × 8AND PACKAGERANGE(MHz)DWG. #ROMP80C52SBPNOTPP87C52SBPN00 to +70, Plastic Dual In-line Packageto+70PlasticDualInlinePackage22.7 V to 5.5 V7Vto55V00 to 16to16SOT129SOT129-11ROMP80C52SBAAOTPP87C52SBAA00 to +70, Plastic Leaded Chip Carrierto+70PlasticLeadedChipCarrier22.7 V to 5.5 V7Vto55V00 to 16to16SOT187SOT187-22ROMP80C52SBBBOTPP87C52SBBB00 to +70, Plastic Quad Flat Packto+70PlasticQuadFlatPack22.7 V to 5.5 V7Vto55V00 to 16to16SOT307SOT307-22ROMP80C52SFPNOTPP87C52SFPN–40 to +85, Plastic Dual In-line Package40to+85PlasticDualInlinePackage22.7 V to 5.5 V7Vto55V00 to 16to16SOT129SOT129-11ROMP80C52SFAAOTPP87C52SFAA–40 to +85, Plastic Leaded Chip Carrier40to+85PlasticLeadedChipCarrier22.7 V to 5.5 V7Vto55V00 to 16to16SOT187SOT187-22ROMP80C52SFBBOTPP87C52SFBB–40 to +85, Plastic Quad Flat Pack40to+85PlasticQuadFlatPack22.7 V to 5.5 V7Vto55V00 to 16to16SOT307SOT307-22ROMP80C52UBAAOTPP87C52UBAA00 to +70, Plastic Leaded Chip Carrierto+70PlasticLeadedChipCarrier55 VV00 to 33to33SOT187SOT187-22ROMP80C52UBPNOTPP87C52UBPN00 to +70, Plastic Dual In-line Packageto+70PlasticDualInlinePackage55 VV00 to 33to33SOT129SOT129-11ROMP80C52UFAAOTPP87C52UFAA–40 to +85, Plastic Leaded Chip Carrier40to+85PlasticLeadedChipCarrier55 VV00 to 33to33SOT187SOT187-22Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 4This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMBLOCK DIAGRAMP0.0–P0.7P2.0–P2.7DRIVERSPORT 0DRIVERSPORT 2VCCVSSRAM ADDRREGISTERRAMPORT 0LATCHPORT 2LATCHROM/EPROM8BREGISTERACCPOINTERSTACKPROGRAMTMP2TMP1REGISTERADDRESSALUBUFFERSFRsPSWTIMERSPCMENTERINCRE-816PROGRAMCOUNTERPSENNOIRALE/PROGTIMINGTCETUSDPTR’SEAVMULTIPLEPPCONTROLANDRITGERSTSNRIPDPORT 1LATCHPORT 3LATCHOSCILLATORDRIVERSPORT 1 DRIVERSPORT 3XTAL1XTAL2P1.0–P1.7P3.0–P3.7SU00845Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 5This Material Copyrighted by Its Respective ManufacturerPhilips Semiconductors80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAMLOGIC SYMBOLVCCVSSXTAL10 ADDRESS ANDTRODATA BUSPXTAL2T2T2EXRST1 TEA/VPPROPSENPSALE/PROGNOIRxDTCTxDNUINT02F3 YINT1 TTRT0RROADDRESS BUSADT1OPPNOWRCERDSSU00830PIN CONFIGURATIONST2/P1.0140VCCT2EX/P1.1239P0.0/AD0P1.2338P0.1/AD1P1.3437P0.2/AD2P1.4536P0.3/AD3P1.5635P0.4/AD4P1.6734P0.5/AD5P1.7833P0.6/AD6RST932P0.7/AD7RxD/P3.010DUALIN-LINE31EA/VPPTxD/P3.111PACKAGE30ALEINT0/P3.21229PSENINT1/P3.31328P2.7/A15T0/P3.41427P2.6/A14T1/P3.51526P2.5/A13WR/P3.61625P2.4/A12RD/P3.71724P2.3/A11XTAL21823P2.2/A10XTAL11922P2.1/A9VSS2021P2.0/A8SU01063Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07This Material Copyrighted by Its Respective ManufacturerProduct specification80C51/87C51/80C52/87C52PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS6140739LCC17291828PinFunctionPinFunctionPinFunction1NIC*16P3.4/T031P2.7/A152P1.0/T217P3.5/T132PSEN3P1.1/T2EX18P3.6/WR33ALE4P1.219P3.7/RD34NIC*5P1.320XTAL235EA/VPP6P1.421XTAL136P0.7/AD77P1.522VSS37P0.6/AD68P1.623NIC*38P0.5/AD59P1.724P2.0/A839P0.4/AD410RST25P2.1/A940P0.3/AD311P3.0/RxD26P2.2/A1041P0.2/AD212NIC*27P2.3/A1142P0.1/AD113P3.1/TxD28P2.4/A1243P0.0/AD014P3.2/INT029P2.5/A1344VCC15P3.3/INT130P2.6/A14* NO INTERNAL CONNECTIONSU01062PLASTIC QUAD FLAT PACK PIN FUNCTIONS4434133PQFP11231222PinFunctionPinFunctionPinFunction1P1.516VSS31P0.6/AD62P1.617NIC*32P0.5/AD53P1.718P2.0/A833P0.4/AD44RST19P2.1/A934P0.3/AD35P3.0/RxD20P2.2/A1035P0.2/AD26NIC*21P2.3/A1136P0.1/AD17P3.1/TxD22P2.4/A1237P0.0/AD08P3.2/INT023P2.5/A1338VCC9P3.3/INT124P2.6/A1439NIC*10P3.4/T025P2.7/A1540P1.0/T211P3.5/T126PSEN41P1.1/T2EX12P3.6/WR27ALE42P1.213P3.7/RD28NIC*43P1.314XTAL229EA/VPP44P1.415XTAL130P0.7/AD7* NO INTERNAL CONNECTIONSU010 6Philips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMPIN DESCRIPTIONSPIN NUMBERMNEMONICDIPLCCQFPTYPENAME AND FUNCTIONVSS202216IGround: 0 V reference.VCC404438IPower Supply: This is the power supply voltage for normal, idle, and power-down operation.P0.0–0.739–3243–3637–30I/OPort 0: Port 0 is an open-drain, bidirectional I/O port with Schmitt trigger inputs. Port 0 pinsthat have 1s written to them float and can be used as high-impedance inputs. Port 0 is alsothe multiplexed low-order address and data bus during accesses to external program anddata memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0also outputs the code bytes during program verification and received code bytes duringEPROM programming. External pull-ups are required during program verification.P1.0–P1.71–82–940–44,I/OPort 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger1–3inputs. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups andcan be used as inputs. As inputs, port 1 pins that are externally pulled low will sourcecurrent because of the internal pull-ups. (See DC Electrical Characteristics: Ireceives the low-order address byte during program memory verification. Alternate functionsIL). Port 1 alsofor Port 1 include:1240I/OT2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out)2341IT2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction controlP2.0–P2.721–2824–3118–25I/OPort 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt triggerinputs. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups andcan be used as inputs. As inputs, port 2 pins that are externally being pulled low will sourcecurrent because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emitsthe high-order address byte during fetches from external program memory and duringaccesses to external data memory that use 16-bit addresses (MOVX @DPTR). In thisapplication, it uses strong internal pull-ups when emitting 1s. During accesses to externaldata memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2special function register. Some Port 2 pins receive the high order address bits duringEPROM programming and verification.P3.0–P3.710–1711,5,I/OPort 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger13–197–13inputs. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups andcan be used as inputs. As inputs, port 3 pins that are externally being pulled low will sourcecurrent because of the pull-ups. (See DC Electrical Characteristics: Ithe special features of the 80C51 family, as listed below:IL). Port 3 also serves10115IRxD (P3.0): Serial input port11137OTxD (P3.1): Serial output port12148IINT0 (P3.2): External interrupt13159IINT1 (P3.3): External interrupt141610IT0 (P3.4): Timer 0 external input151711IT1 (P3.5): Timer 1 external input161812OWR (P3.6): External data memory write strobe171913ORD (P3.7): External data memory read strobeRST9104IReset: A high on this pin for two machine cycles while the oscillator is running, resets thedevice. An internal diffused resistor to VSS permits a power-on reset using only an externalcapacitor to VCC.ALE/PROG303327OAddress Latch Enable/Program Pulse: Output pulse for latching the low byte of theaddress during an access to external memory. In normal operation, ALE is emitted at aconstant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.Note that one ALE pulse is skipped during each access to external data memory. This pin isalso the program pulse input (PROG) during EPROM programming. ALE can be disabled bysetting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.PSEN293226OProgram Store Enable: The read strobe to external program memory. When the device isexecuting code from the external program memory, PSEN is activated twice each machinecycle, except that two PSEN activations are skipped during each access to external datamemory. PSEN is not activated during fetches from internal program memory.EA/VPP313529IExternal Access Enable/Programming Supply Voltage: EA must be externally held lowto enable the device to fetch code from external program memory locations 0000H to0FFFH. If EA is held high, the device executes from internal program memory unless theprogram counter contains an address greater than the on-chip ROM/OTP. This pin alsoreceives the 12.75 V programming supply voltage (VPP) during EPROM programming. Ifsecurity bit 1 is programmed, EA will be internally latched on Reset.XTAL1192115ICrystal 1: Input to the inverting oscillator amplifier and input to the internal clock generatorcircuits.XTAL2182014OCrystal 2: Output from the inverting oscillator amplifier.NOTE:To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5 V or VSS – 0.5 V, respectively.Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 7This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMTable 1. 80C51/87C51/80C52/87C52 Special Function RegistersSYMBOLDESCRIPTIONDIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION RESETADDRESSMSBLSBVALUEACC*AccumulatorE0HE7E6E5E4E3E2E1E000HAUXR#Auxiliary8EH–––––––AOxxxxxxx0BAUXR1#Auxiliary 1A2H–––LPEP2WUPD0–DPSxxx000x0BB*B registerF0HF7F6F5F4F3F2F1F000HDPTR:Data Pointer (2 bytes) DPHData Pointer High83H00H DPLData Pointer Low82H00HAFAEADACABAAA9A8IE*Interrupt EnableA8HEA–ET2ESET1EX1ET0EX00x000000BBFBEBDBCBBBAB9B8IP*Interrupt PriorityB8H––PT2PSPT1PX1PT0PX0xx000000BB7B6B5B4B3B2B1B0IPH#Interrupt Priority HighB7H––PT2HPSHPT1HPX1HPT0HPX0Hxx000000B8786858483828180P0*Port 080HAD7AD6AD5AD4AD3AD2AD1AD0FFH9796959493929190P1*Port 190H––––––T2EXT2FFHA7A6A5A4A3A2A1A0P2*Port 2A0HAD15AD14AD13AD12AD11AD10AD9AD8FFHB7B6B5B4B3B2B1B0P3*Port 3B0HRDWRT1T0INT1INT0TxDRxDFFHPCON#1Power Control87HSMOD1SMOD0–POFGF1GF0PDIDL00xx0000BD7D6D5D4D3D2D1D0PSW*Program Status WordD0HCYACF0RS1RS0OV–P000000x0BRACAP2H#Timer 2 Capture HighCBH00HRACAP2L#Timer 2 Capture LowCAH00HSADDR#Slave AddressA9H00HSADEN#Slave Address MaskB9H00HSBUFSerial Data Buffer99HxxxxxxxxB9F9E9D9C9B9A9998SCON*Serial Control98HSM0/FESM1SM2RENTB8RB8TIRI00HSPStack Pointer81H07H8F8E8D8C8B8A88TCON*Timer Control88HTF1TR1TF0TR0IE1IT1IE0IT000HCFCECDCCCBCAC9C8T2CON*Timer 2 ControlC8HTF2EXF2RCLKTCLKEXEN2TR2C/T2CP/RL200HT2MOD#Timer 2 Mode ControlC9H––––––T2OEDCENxxxxxx00BTH0Timer High 08CH00HTH1Timer High 18DH00HTH2#Timer High 2CDH00HTL0Timer Low 08AH00HTL1Timer Low 18BH00HTL2#Timer Low 2CCH00HTMODTimer ModeHGATEC/TM1M0GATEC/TM1M000HNOTE:Unused register bits that are not defined should not be set by the user’s program. If violated, the device could function incorrectly.*SFRs are bit addressable.#SFRs are modified from or added to the 80C51 SFRs.–Reserved bits.1.Reset value depends on reset source.2.LPEP – Low Power EPROM operation (OTP/EPROM only)Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 8This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMOSCILLATOR CHARACTERISTICSthe SFRs but does not change the on-chip RAM. An externalXTAL1 and XTAL2 are the input and output, respectively, of aninterrupt allows both the SFRs and the on-chip RAM to retain theirinverting amplifier. The pins can be configured for use as an on-chipvalues. WUPD (AUXR1.3–Wakeup from Power Down) enables oroscillator, as shown in the logic symbol.disables the wakeup from power down with external interrupt.To drive the device from an external clock source, XTAL1 should beWhere:driven while XTAL2 is left unconnected. There are no requirementsWUPD = 0 Disableon the duty cycle of the external clock signal, because the input toWUPD = 1 Enablethe internal clock circuitry is through a divide-by-two flip-flop.To properly terminate Power Down the reset or external interruptHowever, minimum and maximum high and low times specified inshould not be executed before Vthe data sheet must be observed.CC is restored to its normaloperating level and must be held active long enough for theResetoscillator to restart and stabilize (normally less than 10 ms).A reset is accomplished by holding the RST pin high for at least twoWith an external interrupt, INT0 or INT1 must be enabled andmachine cycles (24 oscillator periods), while the oscillator is running.configured as level-sensitive. Holding the pin low restarts theTo insure a good power-up reset, the RST pin must be high longoscillator but bringing the pin back high completes the exit. Once theenough to allow the oscillator time to start up (normally a fewinterrupt is serviced, the next instruction to be executed after RETImilliseconds) plus two machine cycles.will be the one following the instruction that put the device intoPower Down.Stop Clock ModeThe static design enables the clock speed to be reduced down toLPEP0 MHz (stopped). When the oscillator is stopped, the RAM andThe eprom array contains some analog circuits that are not requiredSpecial Function Registers retain their values. This mode allowswhen VCC is less than 4 V, but are required for a VCC greater thanstep-by-step utilization and permits reduced system power4 V. The LPEP bit (AUXR.4), when set, will powerdown these analogconsumption by lowering the clock frequency down to any value. Forcircuits resulting in a reduced supply current. This bit should be setlowest power consumption the Power Down mode is suggested.ONLY for applications that operate at a VCC less than 4 V.Idle ModeDesign ConsiderationIn idle mode (see Table 2), the CPU puts itself to sleep while all of•When the idle mode is terminated by a hardware reset, the devicethe on-chip peripherals stay active. The instruction to invoke the idlenormally resumes program execution, from where it left off, up tomode is the last instruction executed in the normal operating modetwo machine cycles before the internal reset algorithm takesbefore the idle mode is activated. The CPU contents, the on-chipcontrol. On-chip hardware inhibits access to internal RAM in thisRAM, and all of the special function registers remain intact duringevent, but access to the port pins is not inhibited. To eliminate thethis mode. The idle mode can be terminated either by any enabledpossibility of an unexpected write when Idle is terminated byinterrupt (at which time the process is picked up at the interruptreset, the instruction following the one that invokes Idle should notservice routine and continued), or by a hardware reset which startsbe one that writes to a port pin or to external memory.the processor in the same manner as a power-on reset.ONCE™ ModePower-Down ModeThe ONCE (“On-Circuit Emulation”) Mode facilitates testing andTo save even more power, a Power Down mode (see Table 2) candebugging of systems without the device having to be removed frombe invoked by software. In this mode, the oscillator is stopped andthe circuit. The ONCE Mode is invoked by:the instruction that invoked Power Down is the last instruction1.Pull ALE low while the device is in reset and PSEN is high;executed. The on-chip RAM and Special Function Registers retain2.Hold ALE low as RST is deactivated.their values down to 2.0 V and care must be taken to return VCC tothe minimum specified operating voltages before the Power DownWhile the device is in ONCE Mode, the Port 0 pins go into a floatMode is terminated.state, and the other port pins and ALE and PSEN are weakly pulledhigh. The oscillator circuit remains active. While the device is in thisFor the 87C51 and 80C51 either a hardware reset or externalmode, an emulator or test CPU can be used to drive the circuit.interrupt can be used to exit from Power Down. Reset redefines allNormal operation is restored when a normal reset is applied.Table 2. External Pin Status During Idle and Power-Down ModesMODEPROGRAM MEMORYALEPSENPORT 0PORT 1PORT 2PORT 3IdleInternal11DataDataDataDataIdleExternal11FloatDataAddressDataPower-downInternal00DataDataDataDataPower-downExternal00FloatDataDataDataPrinted from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 9This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMProgrammable Clock-OutTH2, to be captured into registers RCAP2L and RCAP2H,A 50% duty cycle clock can be programmed to come out on P1.0.respectively. In addition, the transition at T2EX causes bit EXF2 inThis pin, besides being a regular I/O pin, has two alternateT2CON to be set, and EXF2 like TF2 can generate an interruptfunctions. It can be programmed:(which vectors to the same location as Timer 2 overflow interrupt.1.to input the external clock for Timer/Counter 2, orThe Timer 2 interrupt service routine can interrogate TF2 and EXF22.to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz atto determine which event caused the interrupt). The capture mode isa 16 MHz operating frequency.illustrated in Figure 2 (There is no reload value for TL2 and TH2 inthis mode. Even when a capture event occurs from T2EX, theTo configure the Timer/Counter 2 as a clock generator, bit C/T2 (incounter keeps on counting T2EX pin transitions or osc/12 pulses.).T2CON) must be cleared and bit T20E in T2MOD must be set. BitTR2 (T2CON.2) also must be set to start the timer.Auto-Reload Mode (Up or Down Counter)The Clock-Out frequency depends on the oscillator frequency andIn the 16-bit auto-reload mode, Timer 2 can be configured (as eitherthe reload value of Timer 2 capture registers (RCAP2H, RCAP2L)a timer or counter (C/T2* in T2CON)) then programmed to count upas shown in this equation:or down. The counting direction is determined by bit DCEN (DownCounter Enable) which is located in the T2MOD register (seeOscillatorFrequencyFigure 3). When reset is applied the DCEN=0 which means Timer 24 (65536*RCAP2H,RCAP2L)will default to counting up. If DCEN bit is set, Timer 2 can count upor down depending on the value of the T2EX pin.Where:(RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2LFigure 4 shows Timer 2 which will count up automatically sincetaken as a 16-bit unsigned integer.DCEN=0. In this mode there are two options selected by bit EXEN2in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFHIn the Clock-Out mode Timer 2 roll-overs will not generate anand sets the TF2 (Overflow Flag) bit upon overflow. This causes theinterrupt. This is similar to when it is used as a baud-rate generator.Timer 2 registers to be reloaded with the 16-bit value in RCAP2LIt is possible to use Timer 2 as a baud-rate generator and a clockand RCAP2H. The values in RCAP2L and RCAP2H are preset bygenerator simultaneously. Note, however, that the baud-rate and thesoftware means.Clock-Out frequency will be the same.If EXEN2=1, then a 16-bit reload can be triggered either by anoverflow or by a 1-to-0 transition at input T2EX. This transition alsoTIMER 2 OPERATIONsets the EXF2 bit. The Timer 2 interrupt, if enabled, can begenerated when either TF2 or EXF2 are 1.Timer 2In Figure 5 DCEN=1 which enables Timer 2 to count up or down.Timer 2 is a 16-bit Timer/Counter which can operate as either anThis mode allows pin T2EX to control the direction of count. When aevent timer or an event counter, as selected by C/T2* in the speciallogic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 willfunction register T2CON (see Figure 1). Timer 2 has three operatingoverflow at 0FFFFH and set the TF2 flag, which can then generatemodes:Capture, Auto-reload (up or down counting) ,and Baud Ratean interrupt, if the interrupt is enabled. This timer overflow alsoGenerator, which are selected by bits in the T2CON as shown incauses the 16–bit value in RCAP2L and RCAP2H to be reloadedTable 3.into the timer registers TL2 and TH2.Capture ModeWhen a logic 0 is applied at pin T2EX this causes Timer 2 to countIn the capture mode there are two options which are selected by bitdown. The timer will underflow when TL2 and TH2 become equal toEXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer orthe value stored in RCAP2L and RCAP2H. Timer 2 underflow setscounter (as selected by C/T2* in T2CON) which, upon overflowingthe TF2 flag and causes 0FFFFH to be reloaded into the timersets bit TF2, the timer 2 overflow bit. This bit can be used toregisters TL2 and TH2.generate an interrupt (by enabling the Timer 2 interrupt bit in theThe external flag EXF2 toggles when Timer 2 underflows orIE register). If EXEN2= 1, Timer 2 operates as described above, butoverflows. This EXF2 bit can be used as a 17th bit of resolution ifwith the added feature that a 1- to -0 transition at external inputneeded. The EXF2 flag does not generate an interrupt in this modeT2EX causes the current value in the Timer 2 registers, TL2 andof operation.Table 3. Timer 2 Operating ModesRCLK + TCLKCP/RL2TR2MODE00116-bit Auto-reload01116-bit Capture1X1Baud rate generatorXX0(off)Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 10This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAM(MSB)(LSB)TF2EXF2RCLKTCLKEXEN2TR2C/T2CP/RL2SymbolPositionName and SignificanceTF2T2CON.7Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be setwhen either RCLK or TCLK = 1.EXF2T2CON.6Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX andEXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/downcounter mode (DCEN = 1).RCLKT2CON.5Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clockin modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.TCLKT2CON.4Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clockin modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.EXEN2T2CON.3Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negativetransition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 toignore events at T2EX.TR2T2CON.2Start/stop control for Timer 2. A logic 1 starts the timer.C/T2T2CON.1Timer or counter select. (Timer 2)0 = Internal timer (OSC/12)1 = External event counter (falling edge triggered).CP/RL2T2CON.0Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. Whencleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX whenEXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reloadon Timer 2 overflow.SU00728Figure 1. Timer/Counter 2 (T2CON) Control RegisterOSC÷ 12C/T2 = 0TL2TH2(8-bits)(8-bits)TF2C/T2 = 1T2 PinControlTR2CaptureTransitionDetectorTimer 2InterruptRCAP2LRCAP2HT2EX PinEXF2ControlEXEN2SU00066Figure 2. Timer 2 in Capture ModePrinted from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 11This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMT2MODAddress = 0C9HReset Value = XXXX XX00BNot Bit Addressable——————T2OEDCENBit76543210SymbolFunction—Not implemented, reserved for future use.*T2OETimer 2 Output Enable bit.DCENDown Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit isindeterminate.SU00729Figure 3. Timer 2 Mode (T2MOD) Control RegisterOSC÷ 12C/T2 = 0TL2TH2(8-BITS)(8-BITS)C/T2 = 1T2 PINCONTROLTR2RELOADTRANSITIONDETECTORRCAP2LRCAP2HTF2TIMER 2INTERRUPTT2EX PINEXF2CONTROLEXEN2SU00067Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 12This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAM(DOWN COUNTING RELOAD VALUE)FFHFFHTOGGLEEXF2OSC÷12C/T2 = 0OVERFLOWTL2TH2TF2INTERRUPTT2 PINC/T2 = 1CONTROLTR2COUNTDIRECTION1 = UP0 = DOWNRCAP2LRCAP2H(UP COUNTING RELOAD VALUE)T2EX PINSU00730Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)Timer 1OverflowNOTE: OSC. Freq. is divided by 2, not 12.÷ 2OSC÷ 2“0”“1”C/T2 = 0SMODTL2TH2“1”“0”(8-bits)(8-bits)RCLKC/T2 = 1T2 PinControl÷ 16RX ClockTR2“1”“0”ReloadTCLKTransitionDetectorRCAP2LRCAP2H÷ 16TX ClockT2EX PinEXF2Timer 2InterruptControlEXEN2Note availability of additional external interrupt.SU00068Figure 6. Timer 2 in Baud Rate Generator ModePrinted from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 13This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMBaud Rate Generator Modeunder these conditions, a read or write of TH2 or TL2 may not beBits TCLK and/or RCLK in T2CON (Table 3) allow the serial portaccurate. The RCAP2 registers may be read, but should not betransmit and receive baud rates to be derived from either Timer 1 orwritten to, because a write might overlap a reload and cause writeTimer 2. When TCLK= 0, Timer 1 is used as the serial port transmitand/or reload errors. The timer should be turned off (clear TR2)baud rate generator. When TCLK= 1, Timer 2 is used as the serialbefore accessing the Timer 2 or RCAP2 registers.port transmit baud rate generator. RCLK has the same effect for theserial port receive baud rate. With these two bits, the serial port canTable 4 shows commonly used baud rates and how they can behave different receive and transmit baud rates – one generated byobtained from Timer 2.Timer 1, the other by Timer 2.Table 4. Timer 2 Generated Commonly UsedFigure 6 shows the Timer 2 in baud rate generation mode. The baudrate generation mode is like the auto-reload mode, in that a rolloverBaud Ratesin TH2 causes the Timer 2 registers to be reloaded with the 16-bitvalue in registers RCAP2H and RCAP2L, which are preset byBaBaud RatedRateOscOsc FreqFreqTimer 2software.RCAP2HRCAP2L375 K12 MHzFFFFThe baud rates in modes 1 and 3 are determined by Timer 2’soverflow rate given below:9.6 K12 MHzFFD92.8 K12 MHzFFB2Modes1and3BaudRates+Timer2OverflowRate2.4 K12 MHzFF161.2 K12 MHzFEC8The timer can be configured for either “timer” or “counter” operation.30012 MHzFB1EIn many applications, it is configured for “timer” operation (C/T2*=0).11012 MHzF2AFTimer operation is different for Timer 2 when it is being used as a3006 MHzFD8Fbaud rate generator.1106 MHzF957Usually, as a timer it would increment every machine cycle (i.e., 1/12the oscillator frequency). As a baud rate generator, it incrementsSummary Of Baud Rate Equationsevery state time (i.e., 1/2 the oscillator frequency). Thus the baudTimer 2 is in baud rate generating mode. If Timer 2 is being clockedrate formula is as follows:through pin T2(P1.0) the baud rate is:Modes 1 and 3 Baud Rates =BaudRate+Timer2OverflowRateOscillatorFrequency16[32 [65536*(RCAP2H,RCAP2L)]]If Timer 2 is being clocked internally, the baud rate is:Where:(RCAP2H, RCAP2L)= The content of RCAP2H andRCAP2L taken as a 16-bit unsigned integer.BaudRate+fOSC[32 [65536*(RCAP2H,RCAP2L)]]The Timer 2 as a baud rate generator mode shown in Figure 6, isWhere fvalid only if RCLK and/or TCLK = 1 in T2CON register. Note that aOSC= Oscillator Frequencyrollover in TH2 does not set TF2, and will not generate an interrupt.To obtain the reload value for RCAP2H and RCAP2L, the aboveThus, the Timer 2 interrupt does not have to be disabled whenequation can be rewritten as:Timer 2 is in the baud rate generator mode. Also if the EXEN2(T2 external enable flag) is set, a 1-to-0 transition in T2EXRCAP2H,RCAP2L+65536*ǒfOSC(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but32 BaudRateǓwill not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).Therefore when Timer 2 is in use as a baud rate generator, T2EXTimer/Counter 2 Set-upcan be used as an additional external interrupt, if needed.Except for the baud rate generator mode, the values given forT2CON do not include the setting of the TR2 bit. Therefore, bit TR2When Timer 2 is in the baud rate generator mode, one should not trymust be set, separately, to turn the timer on. See Table 5 for set-upto read or write TH2 and TL2. As a baud rate generator, Timer 2 isof Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as aincremented every state time (osc/2) or asynchronously from pin T2;counter.Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 14This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMTable 5. Timer 2 as a TimerMODET2CONINTERNAL CONTROL (Note 1)EXTERNAL CONTROL (Note 2)16-bit Auto-Reload00H08H16-bit Capture01H09HBaud rate generator receive and transmit same baud rate34H36HReceive only24H26HTransmit only14H16HTable 6. Timer 2 as a CounterMODETMODINTERNAL CONTROL (Note 1)EXTERNAL CONTROL (Note 2)16-bit02H0AHAuto-Reload03H0BHNOTES:1.Capture/reload occurs only on timer/counter overflow.2.Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rategenerator mode.Enhanced UARTSADDR are to b used and which bits are “don’t care”. The SADENThe UART operates in all of the usual modes that are described inmask can be logically ANDed with the SADDR to create the “Given”the first section of Data Handbook IC20, 80C51-Based 8-Bitaddress which the master will use for addressing each of the slaves.Microcontrollers. In addition the UART can perform framing errorUse of the Given address allows multiple slaves to be recognizeddetect by looking for missing stop bits, and automatic addresswhile excluding others. The following examples will help to show therecognition. The UART also fully supports multiprocessorversatility of this scheme:communication.Slave 0SADDR= 1100 0000When used for framing error detect the UART looks for missing stopSADEN= 1111 1101bits in the communication. A missing bit will set the FE bit in theGiven=110000X0SCON register. The FE bit shares the SCON.7 bit with SM0 and thefunction of SCON.7 is determined by PCON.6 (SMOD0) (seeSlave 1SADDR= 1100 0000Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7SADEN= 1111 1110functions as SM0 when SMOD0 is cleared. When used as FEGiven=1100000XSCON.7 can only be cleared by software. Refer to Figure 8.In the above example SADDR is the same and the SADEN data isused to differentiate between the two slaves. Slave 0 requires a 0 inAutomatic Address Recognitionbit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 isAutomatic Address Recognition is a feature which allows the UARTignored. A unique address for Slave 0 would be 1100 0010 sinceto recognize certain addresses in the serial bit stream by usingslave 1 requires a 0 in bit 1. A unique address for slave 1 would behardware to make the comparisons. This feature saves a great deal1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can beof software overhead by eliminating the need for the software toselected at the same time by an address which has bit 0 = 0 (forexamine every serial address which passes by the serial port. Thisslave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressedfeature is enabled by setting the SM2 bit in SCON. In the 9 bit UARTwith 1100 0000.modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will beautomatically set when the received byte contains either the “Given”In a more complex system the following could be used to selectaddress or the “Broadcast” address. The 9 bit mode requires thatslaves 1 and 2 while excluding slave 0:the 9th information bit is a 1 to indicate that the received informationSlave 0SADDR= 1100 0000is an address and not data. Automatic address recognition is shownSADEN= 1111 1001in Figure 9.Given=11000XX0The 8 bit mode is called Mode 1. In this mode the RI flag will be setSlave 1SADDR= 1110 0000if SM2 is enabled and the information received has a valid stop bitSADEN= 1111 1010following the 8 address bits and the information is either a Given orGiven=11100X0XBroadcast address.Slave 2SADDR= 1110 0000Mode 0 is the Shift Register mode and SM2 is ignored.SADEN= 1111 1100Using the Automatic Address Recognition feature allows a master toGiven=111000XXselectively communicate with one or more slaves by invoking theIn the above example the differentiation among the 3 slaves is in theGiven slave address or addresses. All of the slaves may belower 3 address bits. Slave 0 requires that bit 0 = 0 and it can becontacted by using the Broadcast address. Two special Functionuniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 andRegisters are used to define the slave’s address, SADDR, and theit can be uniquely addressed by 1110 and 0101. Slave 2 requiresaddress mask, SADEN. SADEN is used to define which bits in thethat bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 15This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52
low power, high speed (33 MHz), 128/256 B RAM
and 1 and exclude Slave 2 use address 1110 0100, since it isUpon reset SADDR (SFR address 0A9H) and SADEN (SFR
necessary to make bit 2 = 1 to exclude slave 2.
address 0B9H) are leaded with 0s. This produces a given addressThe Broadcast Address for each slave is created by taking theof all “don’t cares” as well as a Broadcast address of all “don’t
logical OR of SADDR and SADEN. Zeros in this result are trendedcares”. This effectively disables the Automatic Addressing mode andas don’t-cares. In most cases, interpreting the don’t-cares as ones,allows the microcontroller to use standard 80C51 type UART driversthe broadcast address will be FF hexadecimal.
which do not make use of this feature.
SCON Address = 98HReset Value = 0000 0000B
Bit Addressable
SM0/FE
SM1
SM2RENTB8RB8TlRlBit:
765
4
3
2
1
0
(SMOD0 = 0/1)*
SymbolFunction
FEFraming Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by validframes but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.SM0Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)SM1
Serial Port Mode Bit 1SM0SM1ModeDescriptionBaud Rate**000shift registerfOSC/120118-bit UARTvariable
1029-bit UARTfOSC/ or fOSC/321
1
3
9-bit UART
variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless thereceived 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is aGiven or Broadcast Address. In Mode 0, SM2 should be 0.
RENEnables serial reception. Set by software to enable reception. Clear by software to disable reception.TB8The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
RB8In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used.
TlTransmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in theother modes, in any serial transmission. Must be cleared by software.
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time inthe other modes, in any serial reception (except see SM2). Must be cleared by software.
NOTE:
*SMOD0 is located at PCON6.**fOSC = oscillator frequency
SU00043Figure 7. SCON: Serial Port Control Register
Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 16
This Material Copyrighted by Its Respective Manufacturer
Philips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMD0D1D2D3D4D5D6D7D8START DATA BYTEBITONLY IN MODE 2, 3STOP BITSET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)SM0 TO UART MODE CONTROLSM0 / FESM1SM2RENTB8RB8TIRISCON(98H)SMOD1SMOD0–POFGF1GF0PDIDLPCON(87H)0 : SCON.7 = SM01 : SCON.7 = FESU01191Figure 8. UART Framing Error DetectionD0D1D2D3D4D5D6D7D8SM0SM1SM2RENTB8RB8TIRISCON(98H)1111X10RECEIVED ADDRESS D0 TO D7PROGRAMMED ADDRESSCOMPARATORIN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.SU00045Figure 9. UART Multiprocessor Communication, Automatic Address RecognitionPrinted from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 17This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMInterrupt Priority StructureAn interrupt will be serviced as long as an interrupt of equal orThe 80C51/87C51 and 80C52/87C52 have a 6-source four-levelhigher priority is not already being serviced. If an interrupt of equalinterrupt structure. They are the IE, IP and IPH. (See Figures 10, 11,or higher level priority is being serviced, the new interrupt will waitand 12.) The IPH (Interrupt Priority High) register that makes theuntil it is finished before being serviced. If a lower priority levelfour-level interrupt structure possible. The IPH is located at SFRinterrupt is being serviced, it will be stopped and the new interruptaddress B7H. The structure of the IPH register and a description ofserviced. When the new interrupt is finished, the lower priority levelits bits is shown in Figure 12.interrupt that was stopped will be completed.The function of the IPH SFR is simple and when combined with theIP SFR determines the priority of each interrupt. The priority of eachinterrupt is determined as shown in the following table:PRIORITY BITSIPH.xIP.xINTERRUPTINTERRUPT PRIORITY LEVELPRIORITYLEVEL00Level 0 (lowest priority)01Level 110Level 211Level 3 (highest priority)Table 7. Interrupt TableSOURCEPOLLING PRIORITYREQUEST BITSHARDWARE CLEAR?VECTOR ADDRESSX01IE0N (L)1Y (T)203HT02TP0Y0BHX13IE1N (L)Y (T)13HT14TF1Y1BHSP5RI, TIN23HT26TF2, EXF2N2BHNOTES:1.L = Level activated2.T = Transition activated76543210IE (0A8H)EA—ET2ESET1EX1ET0EX0Enable Bit = 1 enables the interrupt.Enable Bit = 0 disables it.BITSYMBOLFUNCTIONIE.7EAGlobal disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individuallyenabled or disabled by setting or clearing its enable bit.IE.6—Not implemented. Reserved for future use.IE.5ET2Timer 2 interrupt enable bit.IE.4ESSerial Port interrupt enable bit.IE.3ET1Timer 1 interrupt enable bit.IE.2EX1External interrupt 1 enable bit.IE.1ET0Timer 0 interrupt enable bit.IE.0EX0External interrupt 0 enable bit.SU00571Figure 10. IE RegistersPrinted from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 18This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52
low power, high speed (33 MHz), 128/256 B RAM
7
6543210IP (0B8H)
—
—
PT2
PS
PT1
PX1
PT0
PX0
Priority Bit = 1 assigns higher priorityPriority Bit = 0 assigns lower priority
BITSYMBOLFUNCTION
IP.7—Not implemented, reserved for future use.IP.6—Not implemented, reserved for future use.IP.5PT2Timer 2 interrupt priority bit.IP.4PSSerial Port interrupt priority bit.IP.3PT1Timer 1 interrupt priority bit.IP.2PX1External interrupt 1 priority bit.IP.1PT0Timer 0 interrupt priority bit.IP.0
PX0
External interrupt 0 priority bit.
SU00572Figure 11. IP Registers
7
6543210IPH (B7H)
—
—
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Priority Bit = 1 assigns higher priorityPriority Bit = 0 assigns lower priority
BITSYMBOLFUNCTION
IPH.7—Not implemented, reserved for future use.IPH.6—Not implemented, reserved for future use.IPH.5PT2HTimer 2 interrupt priority bit high.IPH.4PSHSerial Port interrupt priority bit high.IPH.3PT1HTimer 1 interrupt priority bit high.IPH.2PX1HExternal interrupt 1 priority bit high.IPH.1PT0HTimer 0 interrupt priority bit high.IPH.0
PX0H
External interrupt 0 priority bit high.
SU01058Figure 12. IPH Registers
Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 19
This Material Copyrighted by Its Respective Manufacturer
Philips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMReduced EMINote that bit 2 is not writable and is always read as a zero. ThisAll port pins of the 8xC51 and 8xC52 have slew rate controlledallows the DPS bit to be quickly toggled simply by executing an INCoutputs. This is to limit noise generated by quickly switching outputDPTR instruction without affecting the WOPD or LPEP bits.signals. The slew rate is factory set to approximately 10 ns rise andfall times.Reduced EMI ModeDPSThe AO bit (AUXR.0) in the AUXR register when set disables theALE output.BIT0AUXR1DPTR1AUXR (8EH)DPTR0DPHDPL76543210(83H)(82H)EXTERNAL–––––––AODATAMEMORYAUXR.0AOTurns off ALE output.SU00745AFigure 13. Dual DPTRThe dual DPTR structure (see Figure 13) enables a way to specifyDPTR Instructionsthe address of an external data memory location. There are twoThe instructions that refer to DPTR refer to the data pointer that is16-bit DPTR registers that address the external memory, and acurrently selected using the AUXR1/bit 0 register. The sixsingle bit called DPS = AUXR1/bit0 that allows the program code toinstructions that use the DPTR are as follows:switch between them.•New Register Name: AUXR1#INC DPTRIncrements the data pointer by 1•SFR Address: A2HMOV DPTR, #data16Loads the DPTR with a 16-bit constant•Reset Value: xxx000x0BMOV A, @ A+DPTRMove code byte relative to DPTR to ACCAUXR1 (A2H)MOVX A, @ DPTRMove external RAM (16-bit address) toACC76543210MOVX @ DPTR , AMove ACC to external RAM (16-bit–––LPEPWUPD0–DPSaddress)Where:JMP @ A + DPTRJump indirect relative to DPTRDPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.Select RegDPSThe data pointer can be accessed on a byte-by-byte basis byspecifying the low or high byte in an instruction which accesses theDPTR00SFRs. See application note AN458 for more details.DPTR11The DPS bit status should be saved by software when switchingbetween DPTR0 and DPTR1.Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 20This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMABSOLUTE MAXIMUM RATINGS1, 2, 3PARAMETERRATINGUNITOperating temperature under bias0 to +70 or –40 to +85°CStorage temperature range–65 to +150°CVoltage on EA/VPP pin to VSS0 to +13.0VVoltage on any other pin to VSS–0.5 to +6.5VMaximum IOL per I/O pin15mAPower dissipation (based on package heat transfer limitations, not device power consumption)1.5WNOTES:1.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only andfunctional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics sectionof this specification is not implied.2.This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive staticcharge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.3.Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwisenoted.AC ELECTRICAL CHARACTERISTICSTamb = 0°C to +70°C or –40°C to +85°CCLOCK FREQUENCYRANGE –fSYMBOLFIGUREPARAMETERMINMAXUNIT1/tCLCL29Oscillator frequencySpeed versions:S (16 MHz)016MHzU (33 MHz)033MHzPrinted from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 21This Material Copyrighted by Its Respective ManufacturerPhilips SemiconductorsProduct specification80C51 8-bit microcontroller family4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52low power, high speed (33 MHz), 128/256 B RAMDC ELECTRICAL CHARACTERISTICSTamb = 0°C to +70°C or –40°C to +85°C, VCC = 2.7 V to 5.5 V, VSS = 0 V (16 MHz devices)SYMBOLPARAMETERTESTLIMITSCONDITIONSMINTYP1MAXUNITVInput low voltageInputlowvoltage114.0 V < VCC < 5.5 V–0.50.2 VCC–0.1VIL2.7 V 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52 low power, high speed (33 MHz), 128/256 B RAM DIP40:plastic dual in-line package; 40 leads (600 mil)SOT129-1 Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 35 This Material Copyrighted by Its Respective Manufacturer Philips SemiconductorsProduct specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52 low power, high speed (33 MHz), 128/256 B RAM PLCC44:plastic leaded chip carrier; 44 leadsSOT187-2 Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 36 This Material Copyrighted by Its Respective Manufacturer Philips SemiconductorsProduct specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), 80C51/87C51/80C52/87C52 low power, high speed (33 MHz), 128/256 B RAM QFP44:plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mmSOT307-2 Printed from www.freetradezone.com, a service of Partminer, Inc.2000 Aug 07 37 This Material Copyrighted by Its Respective Manufacturer Philips SemiconductorsProduct specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM 80C51/87C51/80C52/87C52 Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. Fordetailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above oneor more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these orat any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extendedperiods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. PhilipsSemiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing ormodification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products canreasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applicationsdo so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standardcells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes noresponsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to theseproducts, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unlessotherwise specified. Philips Semiconductors811 East Arques AvenueP.O. Box 3409 Sunnyvale, California 94088–3409Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 08-00 Document order number:9397 750 07404PhilipsSemiconductors2000 Aug 07Printed from www.freetradezone.com, a service of Partminer, Inc.This Material Copyrighted by Its Respective Manufacturer 38
因篇幅问题不能全部显示，请点此查看更多更全内容
Copyright © 2019- baoaiwan.cn 版权所有 赣ICP备2024042794号-3
违法及侵权请联系：TEL:199 18 7713 E-MAIL:2724546146@qq.com
本站由北京市万商天勤律师事务所王兴未律师提供法律服务