大连交通大学2010年COA考试试题及答案

2008～2009 学年 第 1 学期

专 业 装 订

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教研室主任

（签字）

学院院长（系主任）（签字）

课程 Computer Organization and Architecture（B）

（2008年级）

(计算机组织与结构)

课程性质（█必修□专业限选□任选） 考试方式（█闭卷□开卷）

PART A.

Select the best answers based on this course and fill them 得分 into following table.(There are 40 questions in this part，each 1 point，total 40 points)

question answer question answer question answer question answer 1 11 21 31 2 12 22 32 3 13 23 33 4 14 24 34 5 15 25 35 6 16 26 36 7 17 27 37 8 18 28 38 9 19 29 39 10 20 30 40

1. The instruction decoder is located between __________. A. CPU and memory

B. Instruction Register and Control Unit C. registers and ALU

D. Program Counter and Instruction Rigester

2. The most complex instruction execution may include ______cycle(s). A. 4 B. 3 C. 2 D. 1

3. _________ gives the concept of stored program.

A. Bill Gates B. Gordon Moore C. William Stallings D. John von Neumann

4. Pipeline’s performance depends on ______. A. the number of stages B. the length of instruction

C. the number of instructions in instruction set D. the length of operand

5. The main functions of ALU are ______. A. logic operations B. both A & C

C. arithmetic operations D. addition, subtract, multiplication and division 6. In an instruction, source or result operands can not in ______. A. main memory B. CPU register C. I/O D. all of A, B and C

题 号 得 分 1--40 41 42 43 44 45 总 分 7. Some type of instruction limit the pipeline’s performance , the worst one is ____ . A. I/O instructions B. conditional branch instruction

C. Arithmetic instruction D. data transfer instructions 8. The direct addressing mode means ___. A. operand includes in instruction

B. address of operand’s address included in instruction C. operand been unnecessary

D. operand’s address included in instruction

9. The address is known as a type of data, because it is represented by ______. A. a number of floating point B. a signed integer C. an unsigned integer D. a number of decimal

10. If two’s complement 1111 1111 and 1111 1111 are added, the sum in decimal representation is ______. A. –1 . B. –2 C. -126 D. overflow 11. The aim of the indirect cycle is to ________.

A. get an operand B.write a result C. get the address of operand D. fetch an instruction 12. In RAID, __________ is most important.

A. to enlarge capacity of available data in disk system B. to enable the recovery of data lost due to a disk failure C. to find and correct the read/write errors D. to improve I/O request rate of system

13. The 8-bit twos complement 1010 1101 is extended to a 16-bit _____________. A. 0000 0000 0101 0011 B. 1111 1111 1010 1101 C. 0000 0000 1010 1101 D. 1000 0000 0010 1101 14. RAID level(s)_________make use of distributed parity technique. A. 3 B. 4 C. 5 D. all

15. The disadvantage of direct ADDRESSING is ___________ .

A. more memory reference B. large value range C. limit memory address range D. limit value range

16. After an instruction is fetched, the address of the address of next instruction may be in ______ register.

A. MAR B. SP C. AC D. PC

17. DMA means ______.

A. B. C. D.

CPU Directly Manages Address bus “Direct Memory Addressing” mode Another Magnetic Disks

I/O Directly Accesses Memory data

18. On address mapping of cache, any block of main memory must be mapped to fixed set and any line of cache,

it is ___________ .

A． Associative Mapping B。 Direct Mapping C． Set Associative Mapping D。 Random Mapping

19. The access mode of memory system is known as______.

A. sequence access B. random access C. direct access D. associative access 20. Memory cell of 1-transistor and 1-capacitor(电容) is _____________. . A. flash B. static RAM C. EPROM D. dynamic RAM

考生注意： 考试时间 120 分钟 试卷总分 100 分 共 4 页 第 1 页

21. The signals of interrupt request and acknowledgement exchange between CPU and

requesting I/O module. The acknowledgement occurs in __________ cycle。

A. fetch B. indirection C. interruption D. execution

专 业 22. Cache’s write-through polity means write operation to main memory _______.

A. as well as to cache B. only when the cache line is replaced C. when the difference between cache and main memory is found D. only when direct mapping is used

班 级 23. Which type of storage element is non-volatile?

A. ROM B. register C. DRAM D. SRAM

学 号 装 24. If the speed of main memory is as fast as CPU, which technique is not necessary.

A. DMA B. Interrupt C. Cache mapping D. instruction Pipeline

25. There are threekinds of BUSes. Which is not belong to them?

A. address bus B. system bus C. data bus D. control bus

姓 名 订 26. _________ refers to transferring between computer and memory?

A. data movement B. data processing C. data storage D. data control 27. Generally ___________ cache in CPU is(are) divided to Instruction cache and Data cache.

A. L1 B. L2 C. both L1 and L2 D. neither L1 nor L2 28. The ______ register holds points the top of the stack. A. PC B. SP C. MAR D. MBR

29. Before DMA operation, DMA controller must send some signal to CPU for getting the control of BUS, which is called ______________ :

A. DMA request B. interrupt request C. interrupt acknowledgement D. DMA acknowledgement

30. If signed integer is 32-bit, its representation range is _________. A. 0----232-1 B. 1----232 C. -231----231-1 D. –(231-1)---231-1 31. SRAM is used for ___________.

A. CACHE on chip B. CACHE off chip C. main memory D. bath A & B 32. The sequence of interrupt process steps are __________. A. suspending , resuming , branching & processing B. branching , suspending , processing & resuming C. suspending , branching , processing & resuming D. processing , branching , resuming & suspending

33. In index-register addressing mode , the address of operand is equal to ______.

A. The content of base-register plus displacement B. The content of index-register plus displacement

C. The content of program counter plus displacement D. The content of AC plus displacement 34. The SMP means __________.

A. Sharing Memory Processes B. Split Memory to 2 or more Parts C. Stack and Memory Pointer D. Symmetric Multi-Processor 35. Using immediate addressing, after fetch subcycle, __________ in MBR. A. an instruction B. address of an instruction C. an operand D. address of an operand

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36. Hamming code can ___________________ one-bit error in a binary code . A. check out and correct B. check out C. create D. C and B 37. _________ isn’t a register

A. PC B. AC C. MAR D. ALU

38. _________ has the least capacity but the fastest speed. A. registers B. cache C. memory D. magnetic disk

39. Before micro-operation Write->Memory or Read->Memoty , the address must be put in _____. A. MAR B. MBR C. PC D. AC

40. Following two’s complements, _________ is minimum value . A. 1000 0001 B. 1111 1111 C. 0000 0001 D. 0111 1111

PART B. 得分

41. Describe simply all steps of the Interruption . (9 points)

[Sol.] 0. CPU does something……

10.CPU continues doing something……… 共 4 页

第 2 页

42、Suppose the code 1111 1100 0000 is just read from

得分 memory , please use the Hamming algorithm to determine what is the valid 8-bit data? (12 points)

专 业 and data-bit.

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学 号

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NOTE: must give the TRUTH table and the relationship between check-bit 姓 名 订

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得分

43. In multi-processor systems, MESI protocol is used to solve the problem of cache

coherence. (12 points) I S I S

M I

E M E Iniatial Snoopy

1) This is the case of __________________.

2) Please complete this figure.

3) With this case , please fill best answers into following table.

The states in begin Initial snoopy Where is the Valid datd? Actions The states in end Initial snoopy 共 4 页 第 3 页

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得分 专 业 44. Consider a 2-way set associative mapping organization(15

points):

班 级 1. memory size is 256M-Byte 2. cache size is 4M-byte 3. block size is -byte

Please answer following questions:

1. what is address format ?

2． which set can memory address 1e2d3c4H and 7654321H be mapped to?

3. the line with the tag being 88H and the set number being 66H, where can it write 学 号 订 back to ?

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45. Show all the micro-operations for the following instruction: (12 points) 1. SUB R1 ， R2, R3;

— R1, R2 & R3 are registers, subtracts R1 & R2, the result is stored to R3. 2. STORE R2 , (R1) ;

---- Storess an operand from R2 to memory。R1 holds the operand’s address.

得分 共4页 第 4 页

question 1 2 3 4 5 6 7 8 9 10 answer B B D A B D B D C B question 11 12 13 14 15 16 17 18 19 20 answer C B B C C D D B B D question 21 22 23 24 25 26 27 28 29 30 answer C A A C B A A B A C question 31 32 33 34 35 36 37 38 39 40 answer D C B D A A D A A A Ⅱ

0. CPU does something else….

1. I/O module issues an interrupt signal to CPU

2. The CPU finishes execution of the current instruction before responding to the interrupt

3. The CPU tests & makes sure of an interrupt , and sends an acknowledge signal to module ( allows the module to remove its interrupt signal & to sends interrupt number to CPU)

4. The CPU saves information of current program to stack for resuming it. The important information is PSW (running status of current program) & PC(the address of next instruction)

5. The CPU loads new PC value with the entry location of ISR(Interrupt Service Routine) which responds to this interrupt. The CPU must determine the enter location (start address) of ISR by some method based on interrupt number.(Above is completed by HARDWARE.)

(Follow is completed by SOFTWARE(ISR))

6. The CPU begins to execute the instructions of ISR. It saves the remainder(the context of some registers) of program-interrupted onto stack for resuming ….(e.g. AC contains the sum of addition…..)

7. The CPU executes instructions of ISR to process interrupt: tests status of module, fetches data from the module, stores data to memory,….(or fetches data form memory, sends data to device).

8. After service, the CPU prepares to resume the interrupted program, CPU retrieves the remainder from stack & restores them to registers.

9. The CPU executes the last instruction RETI (means return from interrupt), the processing is restoring PSW and PC from stack.

10. The CPU fetches the instruction of the interrupted program by PC & resumes the interrupted program. Ⅲ

The data which read from memory is 1111 1100 0000,

so the data bit is 1111 1000 , the old check bit is 1000According data bit , calculate New check bit C1=D1⊕D2⊕D4⊕D5⊕D7 => C1=0⊕0⊕1⊕1⊕1=1 C2=D1⊕D3⊕D4⊕D6⊕D7 => C1=0⊕0⊕1⊕1⊕1=1 C4=D2⊕D3⊕D4⊕D8 => C1=0⊕0⊕1⊕1=0 C8=D5⊕D6⊕D7⊕D8 => C1=1⊕1⊕1⊕1=0

Old check bit 1000 New check bit ⊕0011 Syndrome word 1011

It means position 11 is error => the valid data is 1011 1000

Ⅳ

1)This is the case of ___write hit ___. 2)Please complete this figure.

3)With this case , please fill best answers into following table.

Iniatial Snoopy I S I S M E M E The states in begin Initial E snoopy I Where is the Valid datd? Initial cache Actions Modify any word The states in end Initial snoopy M I

Ⅴ 1. 7 15 6 2.b4f 150c

3.88h is 8bit but the tag bit is 7bit Ⅵ

1. SUB R1 ， R2, R3;

Fetch cycle Execute cycle t1: (PC) -> MAR t1: (R1) - (R2)-> R3 t2: (MAR) ---> Memory read ---> Memory t3: Memory ---> MBR t4: (MBR) -> IR (PC) +1 -> PC

2. STORE R2 , (R1) ;

Fetch cycle Execute cycle t1: (PC) -> MAR t1: (R1) -> MAR t2: (MAR) ---> Memory

read ---> Memory t2: (MAR) ---> Memory t3: Memory ---> MBR write ---> Memory t4: (MBR) -> IR t3: (R2) ---> Memory (PC) +1 -> PC