HY5DU28822BT-X资料

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HY5DU28422B(L)T HY5DU28822B(L)T

128M-S DDR SDRAM

HY5DU28422B(L)THY5DU28822B(L)T

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.3/May. 02 1

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HY5DU28422B(L)T HY5DU28822B(L)T

Revision History

1. Revision 0.1 (Mar. 02) 1) Define Preliminary Sepcification2. Revision 0.2 (Apr. 02) 1) Change IDD4R/4W Spec.

3. Revision 0.3 (May. 02)

1) Input leakage current changed from +/-5uA to +/-2uA

Rev. 0.3/May. 022

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HY5DU28422B(L)T HY5DU28822B(L)T

DESCRIPTION

PRELIMINARY

The Hynix HY5DU28422B(L)T and HY5DU28822B(L)T are a 134,217,728-bit CMOS Double Data Rate(DDR) Synchro-nous DRAM, ideally suited for the main memory applications which requires large memory density and high band-width.

The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of theclock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatiblewith SSTL_2.

FEATURES

••••••

VDD, VDDQ = 2.5V +/- 0.2V

All inputs and outputs are compatible with SSTL_2 interface

Fully differential clock inputs (CK, /CK) operationDouble data rate interface

Source synchronous - data transaction aligned to bidirectional data strobe (DQS)

Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)

On chip DLL align DQ and DQS transition with CK transition

DM mask write data-in at the both rising and falling edges of the data strobetRAS Lock-out function supported

••••••••

All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock

Programmable /CAS latency 2 and 2.5 supportedProgrammable burst length 2 / 4 / 8 with both sequential and interleave mode

Internal four bank operations with single pulsed /RAS

Auto refresh and self refresh supported4096 refresh cycles / ms

JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch

Full and Half strength driver option controlled by EMRS

•••

ORDERING INFORMATION

Part No.

HY5DU28422B(L)T-X*HY5DU28822B(L)T-X*

OPERATING FREQUENCY

PACKAGE

400mil 66pin TSOP-II

Configuration

32Mx416Mx8

Grade

- J-M- K- H- LCL2

133MHz133MHz133MHz100MHz100MHzCL2.5

166MHz133MHz133MHz133MHz125MHzRemark(CL-tRCD-tRP)

DDR333 (2.5-3-3)DDR266 (2-2-2)DDR266A (2-3-3)DDR266B (2.5-3-3)DDR200 (2-2-2)* X means speed grade

Rev. 0.3/May. 02 3

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HY5DU28422B(L)T HY5DU28822B(L)T

PIN CONFIGURATION(TSOP)

x 4 x 8VDDNCVDDQNCDQ0VSSQNCNCVDDQNCDQ1VSSQNCNCVDDQNCNCVDDNCNC/WE/CAS/RAS/CSNCBA0BA1A10/AP

A0A1A2A3VDD

VDDDQ0VDDQNCDQ1VSSQNCDQ2VDDQNCDQ3VSSQNCNCVDDQNCNCVDDNCNC/WE/CAS/RAS/CSNCBA0BA1A10/AP

A0A1A2A3VDD

1234567101112131415161718192021222324252627282930313233

66656362616059585756555453525150494847454443424140393837363534

x 8 x 4VSSDQ7VSSQNCDQ6VDDQNCDQ5VSSQNCDQ4VDDQNCNCVSSQDQSNCVREFVSSDM/CKCKCKENCNCA11A9A8A7A6A5A4VSS

VSSNCVSSQNCDQ3VDDQNCNCVSSQNCDQ2VDDQNCNCVSSQDQSNCVREFVSSDM/CKCKCKENCNCA11A9A8A7A6A5A4VSS

400mil X 875mil66pin TSOP -II0.65mm pin pitch

ROW AND COLUMN ADDRESS TABLE

ITEMS

OrganizationRow AddressColumn AddressBank AddressAuto Precharge Flag

Refresh

32Mx4

8M x 4 x 4banks

A0 - A11A0-A9, A11BA0, BA1A104K

16Mx8

4M x 8 x 4banks

A0 - A11A0-A9BA0, BA1A104K

Rev. 0.3/May. 024

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HY5DU28422B(L)T HY5DU28822B(L)T

PIN DESCRIPTION

PINCK, /CK

TYPEInput

DESCRIPTION

Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing).Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied.

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-mands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code.

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-CHARGE command is being applied.

Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corre-sponds to the data on DQ8-Q15.

Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.Data input / output pin : Data bus

Power supply for internal circuits and input buffers.Power supply for output buffers for noise immunity.Reference voltage for inputs for SSTL interface.No connection.

CKEInput

/CSInput

BA0, BA1Input

A0 ~ A11Input

/RAS, /CAS, /WEInput

DM (LDM, UDM)

Input

DQS (LDQS, UDQS)

DQVDD/VSSVDDQ/VSSQ

VREFNC

I/OI/OSupplySupplySupplyNC

Rev. 0.3/May. 025

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HY5DU28422B(L)T HY5DU28822B(L)T

FUNCTIONAL BLOCK DIAGRAM (32Mx4)

4Banks x 8Mbit x 4 I/O Double Data Rate Synchronous DRAM

Write Data Register2-bit Prefetch Unit8CLK/CLKCKE/CS/RAS/CAS/WEDMBankControlCommandDecoder8Mx4/Bank0 Sense AMP8Mx4/Bank1 8Mx4/Bank2 8Mx4/Bank3 ModeRegisterRowDecoder84Input BufferOutput Buffer4DS2-bit PrefetchUnitDQ [0:3]Column DecoderADDBA0, BA1DQSAddressBufferColumn Address CounterCLK_DLLDSCLK/CLKDLLBlockData StrobeTransmitterData StrobeReceiverModeRegisterRev. 0.3/May. 026

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HY5DU28422B(L)T HY5DU28822B(L)T

FUNCTIONAL BLOCK DIAGRAM (16Mx8)

4Banks x 4Mbit x 8 I/O Double Data Rate Synchronous DRAM

Write Data Register2-bit Prefetch Unit16CLK/CLKCKE/CS/RAS/CAS/WEDMBankControlCommandDecoder4Mx8/Bank0 Sense AMP4Mx8/Bank1 4Mx8/Bank2 4Mx8/Bank3 ModeRegisterRowDecoder168Input BufferOutput Buffer8DS2-bit PrefetchUnitDQ [0:7]Column DecoderADDBA0,BA1DQSAddressBufferColumn Address CounterCLK_DLLDSCLK/CLKDLLBlockData StrobeTransmitterData StrobeReceiverModeRegisterRev. 0.3/May. 027

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HY5DU28422B(L)T HY5DU28822B(L)T

SIMPLIFIED COMMAND TRUTH TABLE

Command

ExtendedModeRegisterSet

ModeRegisterSetDevice DeselectNoOperationBank ActiveRead

Read with Autoprecharge Write

Write with AutoprechargePrecharge All BanksPrecharge selected Bank

Read Burst StopAutoRefresh Entry

CKEn-1

HHHHH

CKEnXXXXX

CSLLHLLL

RASLLXHLH

CASLLXHHL

WELLXHHH H

CACA

LHLHHLXX

ADDR

A10/APOPcodeOPcode

VVBA

Note1,21,21111,311,41,51111

1111

VXV

HHHHL

XXHLH

LLLLHLHLHLHL

LHLLXHXHXHXV

HHLLXHXHXHXV

LLHHXHXHXHXV

Self Refresh

Exit

Entry

Precharge Power Down Mode

Exit

Active Power Down Mode

EntryExit

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

Note :

1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting duing Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP).

4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written.

5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.

Rev. 0.3/May. 028

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HY5DU28422B(L)T HY5DU28822B(L)T

WRITE MASK TRUTH TABLE

FunctionData WriteData-In Mask

CKEn-1

CKEnXX

/CS, /RAS, /CAS, /WE

DMLH

ADDR

A10/APXX

Note11

Note :

Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.

Rev. 0.3/May. 029

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HY5DU28422B(L)T HY5DU28822B(L)T

OPERATION COMMAND TRUTH TABLE-I

Current State

/CSHLLL

IDLE

LLLLLHLLL

ROWACTIVE

LLLLLHLLL

READ

LLLLLHL

WRITE

LLL

/RASXHHHHLLLLXHHHHLLLLXHHHHLLLLXHHHH

/CASXHHLLHHLLXHHLLHHLLXHHLLHHLLXHHLL

/WEXHLHLHLHLXHLHLHLHLXHLHLHLHLXHLHL

AddressX

XXBA, CA, APBA, CA, APBA, RA

BA,AP

XOPCODE

X BA, CA, APBA, CA, APBA,RABA,APXOPCODE

XXXBA, CA, APBA, CA, APBA,RABA, APXOPCODE

XXXBA, CA, APBA, CA, AP

CommandDSELNOPBSTREAD/READAPWRITE/WRITEAP

ACTPRE/PALLAREF/SREF

MRSDSELNOPBSTREAD/READAPWRITE/WRITEAP

ACTPRE/PALLAREF/SREF

MRSDSELNOPBSTREAD/READAPWRITE/WRITEAP

ACTPRE/PALLAREF/SREF

MRSDSELNOPBSTREAD/READAPWRITE/WRITEAP

Action

NOP or power down3NOP or power down3

ILLEGAL4ILLEGAL4ILLEGAL4Row Activation

NOP

Auto Refresh or Self Refresh5

Mode Register Set

NOPNOPILLEGAL4

Begin read : optional AP6Begin write : optional AP6

ILLEGAL4Precharge7ILLEGAL11ILLEGAL11

Continue burst to endContinue burst to endTerminateburst

Term burst, new read:optional AP8

ILLEGALILLEGAL4

Term burst, precharge

ILLEGAL11ILLEGAL11

Continue burst to endContinue burst to end

ILLEGAL4

Term burst, new read:optional AP8Term burst, new write:optional AP

Rev. 0.3/May. 0210

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HY5DU28422B(L)T HY5DU28822B(L)T

OPERATION COMMAND TRUTH TABLE-II

Current State

/CSL

/RASLLLLXHHHHLLLLXHHHHLLLLXHHHHLLLL

/CASHHLLXHHLLHHLLXHHLLHHLLXHHLLHHLL

/WEHLHLXHLHLHLHLXHLHLHLHLXHLHLHLHL

AddressBA,RABA, AP X

OPCODE

XXX

BA, CA, AP

BA,RABA,APXOPCODE

XBA, CA, APBA, CA, APBA,RABA,APXOPCODE

XXXBA, CA, APBA, CA, APBA,RABA, APXOPCODE

Command

ACTPRE/PALLAREF/SREF

MRSDSELNOPBSTREAD/READAPWRITE/WRITEAP

ACTPRE/PALLAREF/SREF

MRSDSELNOPBSTREAD/READAPWRITE/WRITEAP

ACTPRE/PALLAREF/SREF

MRSDSELNOPBSTREAD/READAPWRITE/WRITEAP

ACTPRE/PALLAREF/SREF

MRS

Action ILLEGAL4Term burst, precharge

ILLEGAL11ILLEGAL11

Continue burst to endContinue burst to end

ILLEGALILLEGAL10ILLEGAL10ILLEGAL4,10ILLEGAL4,10ILLEGAL11ILLEGAL11

Continue burst to endContinue burst to end

ILLEGALILLEGAL10ILLEGAL10ILLEGAL4,10ILLEGAL4,10ILLEGAL11ILLEGAL11

NOP-EnterIDLEaftertRPNOP-Enter IDLE after tRP

ILLEGAL4ILLEGAL4,10ILLEGAL4,10ILLEGAL4,10

NOP-Enter IDLE after tRP

ILLEGAL11ILLEGAL11

WRITE

LLLHLL

READWITHAUTOPRE-CHARGE

LLLLLLHLL

WRITEAUTOPRE-CHARGE

LLLLLLHLLL

PRE-CHARGE

LLLLL

Rev. 0.3/May. 0211

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HY5DU28422B(L)T HY5DU28822B(L)T

OPERATION COMMAND TRUTH TABLE-III

Current State

Address

XXXBA, CA, APBA, CA, AP BA,RA

BA,APXOPCODE

X XBA, CA, APBA, CA, APBA,RABA,APXOPCODE

XXXBA, CA, APBA, CA, APBA,RABA,APXOPCODE

XXXBA, CA, AP

/CSHLLL

/RASXHHHHLLLLXHHHHLLLLXHHHHLLLLXHHH

/CASXHHLLHHLLXHHLLHHLLXHHLLHHLLXHHL

/WEXHLHLHLHLXHLHLHLHLXHLHLHLHLXHLH

CommandDSELNOPBSTREAD/READAPWRITE/WRITEAP

ACTPRE/PALLAREF/SREF

MRSDSELNOPBSTREAD/READAPWRITE/WRITEAP

ACTPRE/PALLAREF/SREF

MRSDSELNOPBSTREAD/READAPWRITE/WRITEAP

ACTPRE/PALLAREF/SREF

MRSDSELNOPBSTREAD/READAP

Action

NOP - Enter ROW ACT after tRCDNOP - Enter ROW ACT after tRCD

ILLEGAL4ILLEGAL4,10ILLEGAL4,10ILLEGAL4,9,10ILLEGAL4,10ILLEGAL11ILLEGAL11

NOP - Enter ROW ACT after tWRNOP - Enter ROW ACT after tWR

ILLEGAL4ILLEGALILLEGALILLEGAL4,10ILLEGAL4,11ILLEGAL11ILLEGAL11

NOP - Enter precharge after tDPLNOP - Enter precharge after tDPL

ILLEGAL4ILLEGAL4,8,10ILLEGAL4,10ILLEGAL4,10ILLEGAL4,11ILLEGAL11ILLEGAL11

NOP - Enter IDLE after tRCNOP - Enter IDLE after tRC

ILLEGAL11ILLEGAL11

ROWACTIVATING

LLLLLHLLL

WRITERECOVERING

LLLLLHLL

WRITERECOVERING

WITHAUTOPRE-CHARGE

LLLLLLHL

REFRESHING

Rev. 0.3/May. 0212

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HY5DU28422B(L)T HY5DU28822B(L)T

OPERATION COMMAND TRUTH TABLE-IV

Current State

/CSLL

WRITE

LLLHLLL

MODEREGISTERACCESSING

LLLLL

/RASHLLLLXHHHHLLLL

/CASLHHLLXHHLLHHLL

/WELHLHLXHLHLHLHL

AddressBA, CA, APBA,RABA,APXOPCODE

BA, CA, APBA, CA, APBA,RABA,APX

OPCODE

CommandWRITE/WRITEAP

ACTPRE/PALLAREF/SREF

MRSDSELNOPBSTREAD/READAPWRITE/WRITEAP

ACTPRE/PALLAREF/SREF

MRS

ActionILLEGAL11ILLEGAL11ILLEGAL11ILLEGAL11ILLEGAL11

NOP - Enter IDLE after tMRDNOP - Enter IDLE after tMRD

ILLEGAL11ILLEGAL11ILLEGAL11ILLEGAL11ILLEGAL11ILLEGAL11ILLEGAL11

Note :

1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,

BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation. 2. All entries assume that CKE was active(high level) during the preceding clock cycle.3. If both banks are idle and CKE is inactive(low level), then in power down mode.

4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of that bank.

5. If both banks are idle and CKE is inactive(low level), then self refresh mode.6. Illegal if tRCD is not met. 7. Illegal if tRAS is not met.

8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.9. Illegal if tRRD is not met.

10. Illegal for single bank, but legal for other banks in multi-bank devices.11. Illegal for all banks.

Rev. 0.3/May. 0213

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HY5DU28422B(L)T HY5DU28822B(L)T

CKE FUNCTION TRUTH TABLE

Current State

CKEn-1HL

SELFREFRESH1

LLLLLHL

POWER DOWN2

LLLLLHHH

ALL BANKS IDLE4

HHHHHL

ANY STATE OTHERTHAN ABOVE

HHLL

CKEnXHHHHHLXHHHHHLHLLLLLLLLHLHL

/CSXHLLLLXXHLLLLXXLHLLLLLXXXXX

/RASXXHHHLXXXHHHLXXLXHHHLLXXXXX

/CASXXHHLXXXXHHLXXXLXHHLHLXXXXX

/WEXXHLXXXXXHLXXXXHXHLXXLXXXXX

/ADDXXXXXXXXXXXXXXXXXXXXXXXXXXX

ActionINVALID

Exit self refresh, enter idle after tSREXExit self refresh, enter idle after tSREX

ILLEGALILLEGALILLEGAL

NOP,continueselfrefresh INVALID

Exit power down, enter idleExit power down, enter idle

ILLEGALILLEGALILLEGAL

NOP, continue power down modeSee operation command truth table

EnterselfrefreshExit power downExit power down

ILLEGALILLEGALILLEGALILLEGALNOP

See operation command truth table

ILLEGAL5INVALIDINVALID

Note :

When CKE=L, all DQ and DQS must be in Hi-Z state.

1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.2. All command can be stored after 2 clocks from low to high transition of CKE.3. Illegal if CLK is suspended or stopped during the power down mode.4. Self refresh can be entered only from the all banks idle state.

5. Disabling CLK may cause malfunction of any bank which is in active state.

Rev. 0.3/May. 0214

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HY5DU28422B(L)T HY5DU28822B(L)TSIMPLIFIED STATE DIAGRAMMODEREGISTER SETMRSIDLESREFSREXSELFREFRESHPDENPDEXPOWERDOWNPOWERDOWNPDEXPDENBSTBANKACTIVEACTAREFAUTOREFRESHREADWRITEPRE(PALL)READAPWRITEWRITEAPWRITEWITHAUTOPRE-CHARGEREADREADAPWITHAUTOPRE-CHARGEWRITEAPREADREADWRITEPRE(PALL)PRE(PALL)PRE-CHARGEPOWER-UPCommand InputAutomatic SequencePOWER APPLIEDRev. 0.3/May. 0215 元器件交易网www.cecb2b.com

HY5DU28422B(L)T HY5DU28822B(L)T

POWER-UP SEQUENCE AND DEVICE INITIALIZATION

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than thosespecified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF(and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent dam-age to the device. VREF can be applied anytime after VDDQ, but is expected to be nominally coincident with VTT.Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detectan LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required toguarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal oper-ation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDRSDRAM requires a 200us delay prior to applying an executable command.

Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should bebrought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDEDMODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODEREGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operatingparameters. 200 clock cycles are required between the DLL reset and any command. During the 200 cycles of CK, forDLL locking, executable commands are disallowed (a DESELECT or NOP command must be applied). After the 200clock cycles, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET commandfor the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting theDLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.1.

Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-MOS low state. (All the other input pins may be undefined.)•VDD and VDDQ are driven from a single power converter output.

•VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation.•VREF tracks VDDQ/2.

•A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the VTT supply into any pin.•If the above criteria cannot be met by the system design, then the following sequencing and voltage relation-ship must be adhered to during power up.

Voltage description

VDDQVTTVREF

2.3.4.5.6.

SequencingAfter or with VDDAfter or with VDDQAfter or with VDDQ

Voltage relationship to avoid latch-up

< VDD + 0.3V< VDDQ + 0.3V< VDDQ + 0.3V

Start clock and maintain stable clock for a minimum of 200usec.After stable power and clock, apply NOP condition and take CKE high.Issue Extended Mode Register Set (EMRS) to enable DLL.

Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles of clock are required for locking DLL)

Issue Precharge commands for all banks of the device.

Rev. 0.3/May. 02

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HY5DU28422B(L)T HY5DU28822B(L)T

7.8.

Issue 2 or more Auto Refresh commands.

Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.

Power-Up SequenceVDDVDDQVTTVREFtVTD≈/CLKCLK≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈tIStIHCKECMD≈≈≈≈≈≈NOPPREEMRSMRSNOPPREAREFMRSDMADDRA10BA0,BA1CODECODECODECODECODECODECODECODECODE≈≈≈≈≈≈≈≈≈≈DQSDQ’sT=200usectRPtMRD200 cycles of CK*tRPtRFCPower upVDD and CK stablePrecharge AllEMRS SetMRS SetReset DLL(with A8=H)Precharge All2 or moreAuto RefreshMRS Set(with A8=L)*200 cycles of CK are required (for DLL locking) before any executable command can be applied.Rev. 0.3/May. 0217

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HY5DU28422B(L)T HY5DU28822B(L)T

MODE REGISTER SET (MRS)

The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by thelow signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state andCKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required towrite the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field isdetermined, the information will be held until resetted by another MRS command.

BA10

BA00

A11A10RFU

A9A8DR

A7TM

A6A5A4A3BT

A2A1A0

CAS LatencyBurst Length

BA001

MRS TypeMRSEMRS

A701

Test ModeNormalVendor Test Mode

Burst Length

Sequential

InterleaveReserved

248ReservedReservedReservedReserved

A801

DLL Reset

Yes

110011

010101

48ReservedReservedReservedReserved

Reserved

A600001111

A500110011

A401010101

CAS LatencyReservedReserved

2ReservedReservedReserved2.5Reserved

A301

01111

Burst TypeSequentialInterleave

Rev. 0.3/May. 0218

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HY5DU28422B(L)T HY5DU28822B(L)T

BURST DEFINITION

Burst Length

Starting Address (A2,A1,A0)

XX0XX1X00

X01X10X11000001010

011100101110111

Sequential0, 11, 00, 1, 2, 31, 2, 3, 02, 3, 0, 13, 0, 1, 20, 1, 2, 3, 4, 5, 6, 71, 2, 3, 4, 5, 6, 7, 02, 3, 4, 5, 6, 7, 0, 13, 4, 5, 6, 7, 0, 1, 24, 5, 6, 7, 0, 1, 2, 35, 6, 7, 0, 1, 2, 3, 46, 7, 0, 1, 2, 3, 4, 50, 1, 2, 3, 4, 5, 6, 7

0, 11, 00, 1, 2, 31, 0, 3, 22, 3, 0, 13, 2, 1, 0

0, 1, 2, 3, 4, 5, 6, 71, 0, 3, 2, 5, 4, 7, 62, 3, 0, 1, 6, 7, 4, 53, 2, 1, 0, 7, 6, 5, 44, 5, 6, 7, 0, 1, 2, 35, 4, 7, 6, 1, 0, 3, 26, 7, 4, 5, 2, 3, 0, 17, 6, 5, 4, 3, 2, 1, 0

Interleave

BURST LENGTH & TYPE

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burstlength determines the maximum number of column locations that can be accessed for a given Read or Write com-mand. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.Reserved states should not be used, as unknown operation or incompatibility with future versions may result.When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. Allaccesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary isreached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A 2 -Ai when the burst lengthis set to four and by A 3 -Ai when the burst length is set to eight (where Ai is the most significant column address bitfor a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting locationwithin the block. The programmed burst length applies to both Read and Write bursts.

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as theburst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, theburst type and the starting column address, as shown in Burst Definitionon Table

Rev. 0.3/May. 0219

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HY5DU28422B(L)T HY5DU28822B(L)T

CAS LATENCY

The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and theavailability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincidentwith clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

DLL RESET

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automaticallydisabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Anytime the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externallyapplied clock before an any command can be issued.

OUTPUT DRIVER IMPEDANCE CONTROL

The normal drive strength for all outputs is specified to be SSTL_2, Class II. Hynix also supports a half strength driveroption, intended for lighter load and/or point-to-point environments. Selection of the half strength driver option willreduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driverand the half strength driver are included in this document.

Rev. 0.3/May. 0220

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HY5DU28422B(L)T HY5DU28822B(L)T

EXTENDED MODE REGISTER SET (EMRS)

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func-tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0) and will retain the stored information until it is programmed again or the device loses power.

The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controllermust wait the specified time before initiating any subsequent operation. Violating either of these requirements willresult in unspecified operation.

BA10

BA01

A11

A10

A7RFU*

A20**

A1DS

A0DLL

BA001

MRS TypeMRSEMRS

A001

DLL enableEnableDiable

A101

Output Driver Impedance ControlFull Strength DriverHalf Strength Driver

* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage** This part do not support /QFC function, A2 must be programmed to Zero.

Rev. 0.3/May. 0221

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HY5DU28422B(L)T HY5DU28822B(L)T

ABSOLUTE MAXIMUM RATINGS

Parameter

Ambient TemperatureStorage Temperature

Voltage on Any Pin relative to VSSVoltage on VDD relative to VSSVoltage on VDDQ relative to VSSOutput Short Circuit CurrentPower Dissipation

Soldering Temperature ⋅ Time

Symbol

TATSTGVIN, VOUT

VDDVDDQIOSPDTSOLDER

Rating

0 ~ 70-55 ~ 125-0.5 ~ 3.6-0.5 ~ 3.6-0.5 ~ 3.6

501260 ⋅ 10

Unit

VVVmAWC ⋅ sec

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)

Parameter

Power Supply VoltagePower Supply VoltageInput High VoltageInput Low VoltageTermination VoltageReference Voltage

Symbol

VDDVDDQVIHVILVTTVREF

Min

2.32.3VREF + 0.15

-0.3VREF - 0.040.49*VDDQ

Typ.

2.52.5--VREF0.5*VDDQ

Max

2.72.7VDDQ + 0.3VREF - 0.15VREF + 0.040.51*VDDQ

Unit

VVVVVV

Note

Note :

1. VDDQ must not exceed the level of VDD.

2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to peak noise on VREF may not exceed +/- 2% of the dc value.

DC CHARACTERISTICS I (TA=0 to 70°C, Voltage referenced to VSS = 0V)

Parameter

Input Leakage CurrentOutput Leakage CurrentOutput High VoltageOutput Low Voltage

Symbol

ILIILOVOHVOL

Min.

-2-5VTT + 0.76

Max

25-VTT - 0.76

Unit

uAuAVV

Note

IOH = -15.2mAIOL = +15.2mA

Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V. 2. DOUT is disabled, VOUT=0 to 2.7VRev. 0.3/May. 02

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HY5DU28422B(L)T HY5DU28822B(L)T

DC CHARACTERISTICS II (TA=0 to 70 oC, Voltage referenced to VSS = 0V)

32Mx4 / 16Mx8

Parameter

Symbol

Test Condition

One bank; Active - Precharge;

tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle

One bank; Active - Read - Precharge; Burst=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle

All banks idle; Power down mode; CKE=Low, tCK=tCK(min)

/CS=High, All banks idle; tCK=tCK(min); CKE=High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DMOne bank active; Power down mode ; CKE=Low, tCK=tCK(min)

/CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle

Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA

Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle;

tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle

tRC=tRFC(min) - 8*tCK for DDR200 at

100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refreshCKE=<0.2V; External clock on; tCK=tCK(min)

NormalLow Power

Speed

-J

-M

-K

-H

-L

UnitNote

Operating CurrentIDD09080808080mA

Operating CurrentIDD111010010010080mA

Precharge Power Down Standby Current

IDD2P2015151515mA

Idle Standby CurrentIDD2F4035353530mA

Active Power Down Standby Current

IDD3P2020202020mA

Active Standby Current

IDD3N4040404040mA

Operating Current IDD4R230190190190150mA

Operating Current IDD4W230190190190150mA

Auto Refresh CurrentIDD5160150150150140mAmAmAmA

Self Refresh CurrentOperating Current - Four Bank Operation

IDD6

21300

21260

21220

IDD7

Four bank interleaving with BL=4, Refer to the following page for detailed test condition

Rev. 0.3/May. 0223

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HY5DU28422B(L)T HY5DU28822B(L)T

DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7IDD1 : Operating current: One bank operation

1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA2. Timing patterns

- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=2, tRCD = 2*tCK, tRAS = 5*tCK

Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing - DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=2, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=2, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst

- DDR266(133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=2, tRCD = 2*tCK, tRC = 8*tCK, tRAS = 6*tCK Read : A0 N R0 N N N P0 N A0 N - repeat the same timing with random address changing 50% of data changing at every burst

- DDR333(166Mhz, CL=2.5) : tCK = 6ns, CL=2, BL=2, tRCD = 3*tCK, tRC = 10*tCK, tRAS = 7*tCK Read : A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

IDD7 : Operating current: Four bank operation

1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA2. Timing patterns

- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst

- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst

- DDR333(166Mhz, CL=2.5) : tCK = 6ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

Rev. 0.3/May. 0224

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HY5DU28422B(L)T HY5DU28822B(L)T

AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)

Parameter

Input High (Logic 1) Voltage, DQ, DQS and DM signalsInput Low (Logic 0) Voltage, DQ, DQS and DM signalsInput Differential Voltage, CK and /CK inputsInput Crossing Point Voltage, CK and /CK inputs

SymbolVIH(AC)VIL(AC)VID(AC)VIX(AC)

0.70.5*VDDQ-0.2

MinVREF + 0.31

VREF - 0.31VDDQ + 0.60.5*VDDQ+0.2

Max

UnitVVVV

12Note

Note :

1. VID is the magnitude of the difference between the input level on CK and the input on /CK.

2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Parameter

Reference VoltageTermination Voltage

AC Input High Level Voltage (VIH, min)AC Input Low Level Voltage (VIL, max)

Input Timing Measurement Reference Level VoltageOutput Timing Measurement Reference Level VoltageInput Signal maximum peak swingInput minimum Signal Slew RateTermination Resistor (RT)Series Resistor (RS)

Output Load Capacitance for Access Time Measurement (CL)

ValueVDDQ x 0.5VDDQ x 0.5VREF + 0.31VREF - 0.31VREFVTT1.51502530

UnitVVVVVVVV/nsΩΩpF

Rev. 0.3/May. 0225

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HY5DU28422B(L)T HY5DU28822B(L)T

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

Parameter

Row Cycle Time

Auto Refresh Row Cycle TimeRow Active Time

Active to Read with Auto Precharge DelayRow Address to Column Address DelayRow Active to Row Active Delay

Column Address to Column Address DelayRow Precharge TimeWrite Recovery Time

Write to Read Command Delay

Auto Precharge Write Recovery + Precharge Time

CL = 2.5CL = 2

SymboltRCtRFCtRAStRAPtRCDtRRDtCCDtRPtWRtWTRtDAL

DDR333Min607242181812118151

(tWR/tCK)

+(tRP/tCK)

DDR266(2-2-2)Min607545151515115151

(tWR/tCK)

+(tRP/tCK)

Max--70K--------12120.550.550.70.60.45--0.55

Max--120K--------12120.550.550.750.750.5--0.75

UnitNote

nsnsnsnsnsnsCKnsnsCKCKnsnsCKCKnsnsnsnsnsnsnsnsnsnsnsns

System Clock Cycle TimeClock High Level WidthClock Low Level Width

Data-Out edge to Clock edge SkewDQS-Out edge to Clock edge Skew

tCKtCHtCLtACtDQSCKtDQSQtQHtHPtQHStDVtHZtLZtIStIHtIS

67.50.450.45-0.7-0.6-tHP-tQHSmin(tCL,tCH)

7.57.50.450.45-0.75-0.75-tHP-tQHSmin(tCL,tCH)

DQS-Out edge to Data-Out edge SkewData-Out hold time from DQSClock Half PeriodData Hold Skew FactorValid Data Output Window

Data-out high-impedance window from CK, /CKData-out low-impedance window from CK, /CKInput Setup Time (fast slew rate)Input Hold Time (fast slew rate)Input Setup Time (slow slew rate)

1,101,910

tQH-tDQSQ-0.7-0.70.750.750.8

0.70.7---

tQH-tDQSQ-0.75-0.750.90.91.0

0.750.75---

17172,3,5,62,3,5,62,4,5,6

Rev. 0.3/May. 0226

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HY5DU28422B(L)T HY5DU28822B(L)T

DDR333Min0.82.20.350.350.750.450.451.750.90.400.250.42200---1.25---1.10.6--0.6--15.6Max-DDR266(2-2-2)Min1.02.20.350.350.720.50.51.750.90.400.250.42200---1.28---1.10.6--0.6--15.6Max-

Parameter

Input Hold Time (slow slew rate)Input Pulse Width

Write DQS High Level WidthWrite DQS Low Level WidthClock to First Rising edge of DQS-InData-In Setup Time to DQS-In (DQ & DM)Data-in Hold Time to DQS-In (DQ & DM)DQ & DM Input Pulse WidthRead DQS Preamble TimeRead DQS Postamble TimeWrite DQS Preamble Setup TimeWrite DQS Preamble Hold TimeWrite DQS Postamble TimeMode Register Set Delay

Exit Self Refresh to Any Execute CommandAverage Periodic Refresh Interval

SymboltIHtIPWtDQSHtDQSLtDQSStDStDHtDIPWtRPREtRPSTtWPREStWPREHtWPSTtMRDtXSCtREFI

UnitNote

nsnsCKCKCKnsnsnsCKCKCKCKCKCKCKus

2,4,5,66

6,7, 11~136,7, 11~13

Rev. 0.3/May. 0227

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HY5DU28422B(L)T HY5DU28822B(L)T

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

Parameter

Row Cycle Time

Auto Refresh Row Cycle TimeRow Active Time

Active to Read with Auto Precharge DelayRow Address to Column Address DelayRow Active to Row Active Delay

Column Address to Column Address DelayRow Precharge TimeWrite Recovery Time

Write to Read Command DelayAuto Precharge Write Recovery + Precharge TimeSystem Clock Cycle Time

Clock High Level WidthClock Low Level Width

Data-Out edge to Clock edge SkewDQS-Out edge to Clock edge SkewDQS-Out edge to Data-Out edge SkewData-Out hold time from DQSClock Half PeriodData Hold Skew FactorValid Data Output Window

Data-out high-impedance window from CK, /CK

Data-out low-impedance window from CK, /CK

CL = 2.5CL = 2

SymboltRCtRFCtRAStRAPtRCDtRRDtCCDtRPtWRtWTRtDAL

DDR266AMin657545202015120151

(tWR/tCK)

+(tRP/tCK)

DDR266BMin657545202015120151

(tWR/tCK)

+(tRP/tCK)

DDR200Min708050202015120151

(tWR/tCK)

+(tRP/tCK)

Max--120K--------12120.550.550.750.750.5--0.75

Max--120k--------12120.550.550.80.80.6--0.75

UnitNote

nsnsnsnsnsnsCKnsnsCKCKnsns

tCKtCHtCLtACtDQSCKtDQSQtQHtHPtQHStDVtHZtLZ

7.57.50.450.45-0.75-0.75-tHP-tQHSmin(tCL,tCH)

7.5100.450.45-0.75-0.75-tHP-tQHSmin(tCL,tCH)

8.0100.450.45-0.8-0.8-tHP-tQHSmin(tCL,tCH)

CKCKnsnsnsnsnsnsnsnsns

17171,101,910

tQH-tDQSQ-0.75-0.75

0.750.75

tQH-tDQSQ-0.75-0.75

0.750.75

tQH-tDQSQ-0.8-0.8

0.80.8

Rev. 0.3/May. 0228

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HY5DU28422B(L)T HY5DU28822B(L)T

-continued-DDR266AMin0.90.91.01.02.20.350.350.750.50.51.750.90.400.250.42200---1.25---1.10.6--0.6--15.6Max----DDR266BMin0.90.91.01.02.20.350.350.750.50.51.750.90.400.250.42200---1.25---1.10.6--0.6--15.6Max----DDR200Min1.11.11.11.12.50.350.350.750.60.620.90.400.250.42200-Max-------1.25---1.10.6--0.6--15.6

Parameter

Input Setup Time (fast slew rate)Input Hold Time (fast slew rate)Input Setup Time (slow slew rate)Input Hold Time (slow slew rate)Input Pulse Width

Exit Self Refresh to Any Execute CommandAverage Periodic Refresh Interval

SymboltIStIHtIStIHtIPWtDQSHtDQSLtDQSStDStDHtDIPWtRPREtRPSTtWPREStWPREHtWPSTtMRDtXSCtREFI

UnitNote

nsnsnsnsnsCKCKCKnsnsnsCKCKCKCKCKCKCKus

2,3,5,62,3,5,62,4,5,62,4,5,66

6,7, 11~13

Rev. 0.3/May. 0229

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HY5DU28422B(L)T HY5DU28822B(L)T

Note :1.2.3.4.

This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.For command/address input slew rate>=1.0V/ns

For command/address input slew rate>=0.5V/ns and <1.0V/ns

This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table.

Input Setup / Hold Slew-rate

V/ns0.50.40.3

5.6.7.8.9.

CK, /CK slew rates are>=1.0V/ns

These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation.

Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.

Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).

Delta tISps0+50+100

Delta tIHps000

10.tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of

tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to n-channel variation of the output drivers.11.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

Input Setup / Hold Slew-rate

V/ns0.50.40.3

Delta tDS

ps0+75+150

Delta tDH

ps0+75+150

12.I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF

+/-310mV for a duration of up to 2ns.

I/O Input Level

mV+280

Delta tDS

ps+50

Delta tDH

ps+50

13.I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and

DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1=

0.5V/ns and Slew Rate2=0.4V/n then the Delta Inverse Slew Rate=-0.5ns/V.

(1/SlewRate1)-(1/SlewRate2)ns/V0+/-0.25+/- 0.5

Delta tDSps0+50+100

Delta tDHps0+50+100

Rev. 0.3/May. 0230

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HY5DU28422B(L)T HY5DU28822B(L)T

14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic.

15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. Example: For DDR266B at CL=2.5 and tCK = 7.5 ns, tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)

Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clocks

16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - (BL/2) x tCK.

17. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).

Rev. 0.3/May. 0231

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HY5DU28422B(L)T HY5DU28822B(L)T

CAPACITANCE (TA=25oC, f=100MHz )

Parameter

Input Clock CapacitanceDelta Input Clock CapacitanceInput CapacitanceDelta Input CapacitanceInput / Output CapacitanceDelta Input / Output Capacitance

CK, /CKCK, /CK

All other input-only pinsAll other input-only pinsDQ, DQS, DMDQ, DQS, DM

SymbolCI1Delta CI1

CI1Delta CI2CIODelta CIO

Min2.0-2.0-4.0-Max3.00.253.00.55.00.5

UnitpFpFpFpFpFpF

Note :

1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V2. Pins not under test are tied to GND.

3. These values are guaranteed by design and are tested on a sample basis only.

OUTPUT LOAD CIRCUIT

VTTRT=50ΩOutputZo=50ΩVREFCL=30pFRev. 0.3/May. 0232

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HY5DU28422B(L)T HY5DU28822B(L)T

PACKAGE INFORMATION

400mil 66pin Thin Small Outline Package

Unit : mm(Inch)11.94 (0.470)11.79 (0.462)10.26 (0.404)10.05 (0.396)BASE PLANE22.33 (0.879)22.12 (0.871)0 ~ 5 Deg.0.65 (0.0256) BSC0.35 (0.0138)0.25 (0.0098)SEATING PLANE0.15 (0.0059)0.05 (0.0020)0.597 (0.0235)0.406 (0.0160)0.210 (0.0083)0.120 (0.0047)1.194 (0.0470)0.991 (0.0390)Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm.

Rev. 0.3/May. 0233

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