MT8808资料

®ISO-CMOSMT88088x8AnalogSwitchArray

Features

••••••••••

Internal control latches and address decoderShort set-up and hold times

Wide operating voltage: 4.5V to 13.2V12Vpp analog signal capabilityRON 65Ω max. @ VDD=12V, 25°C∆RON ≤ 10Ω @ VDD=12V, 25°CFull CMOS switch for low distortionMinimum feedthrough and crosstalk

Separate analog and digital reference suppliesLow power consumption ISO-CMOS technology

ISSUE 2November 1988

Ordering Information

MT8808AC28 Pin Ceramic DIPMT8808AE28 Pin Plastic DIPMT8808AP28 Pin PLCC

-40° to 85°C

Description

The Mitel MT8808 is fabricated in MITEL’s ISO-CMOS technology providing low power dissipationand high reliability. The device contains a 8 x 8 arrayof crosspoint switches along with a 6 to linedecoder and latch circuits. Any one of the switches can be addressed by selecting theappropriate six address bits. The selected switch canbe turned on or off by applying a logical one or zeroto the DATA input. VSS is the ground reference ofthe digital inputs. The range of the analog signalis from VDD to VEE.

Applications

••••••

Key systemsPBX systemsMobile radio

Test equipment /instrumentationAnalog/digital multiplexersAudio/Video switching

STROBEDATARESETVDDVEEVSS

1

AX0AX1AX2AY0AY1AY2

1

• • • • • • • • • • • • • • • •6 to Decoder

8 x 8

Latches

SwitchArray

Xi I/O(i=0-7)

• • • • • • • • • • • • • • • • • • •

Yi I/O (i=0-7)

Figure 1 - Functional Block Diagram

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MT8808

ISO-CMOS

AY2STROBE

VEEDATAVSSX0X2X4X6RESET

Y7Y6Y5Y4123456710111213142827262524232221201918171615

AY1AY0AX2AX1AX0X1X3X5X7VDDY0Y1Y2Y3

4321282726•

DATAVEESTROBEAY2AY1AY0AX228 PIN CERDIP/PLASTIC DIPFigure 2 - Pin Connections

Pin Description

Pin #12

NameAY2

AY2 Address Line (Input).

Description

STROBESTROBE (Input): enables function selected by address and data. Address must be stable

before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High.VEEDATAVSSX0, X2,X4, X6RESETY7 - Y0VDDX7, X5,X3, X1AX0-AX2

Negative Power Supply.

DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High.Digital Ground Reference .

X0, X2, X4 and X6 Analog (Inputs/Outputs): these are connected to the X0, X2, X4 and X6 rows of the switch array.

Master RESET (Input): this is used to turn off all switches. Active High.

Y7 - Y0 Analog (Inputs/Outputs): these are connected to the Y0 - Y7 columns of the switch array.

Positive Power Supply.

X7, X5, X3 and X1 Analog (Inputs/Outputs): these are connected to the X7, X5, X3 and X1 rows of the switch array.

AX0 - AX2 Address Lines (Inputs).

3456-91011-181920-2324-2627,28

AY0, AY1 AY0 and AY1 Address Lines (Inputs).

3-16

Y6Y5Y4Y3Y2Y1Y012131415161718VSSX0X2X4X6RESET

Y7567101125242322212019

AX1AX0X1X3X5X7VDD

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Functional Description

The MT8808 is an analog switch matrix with an arraysize of 8 x 8. The switch array is arranged such thatthere are 8 columns by 8 rows. The columns arereferred to as the Y inputs/outputs and the rows arethe X inputs/outputs. The crosspoint analog switcharray will interconnect any X I/O with any Y I/O whenturned on and provide a high degree of isolationwhen turned off. The control memory consists of a bit write only RAM in which the bits are selected bythe address inputs (AY0-AY2, AX0-AX2). Data ispresented to the memory on the DATA input. Data isasynchro-nously written into memory whenever theSTROBE input is high and is latched on the fallingedge of STROBE. A logical “1” written into a memorycell turns the corresponding crosspoint switch onand a logical “0” turns the crosspoint off. Only thecrosspoint switches corresponding to the addressedmemory location are altered when data is written intomemory. The remaining switches retain theirprevious states. Any combination of X and Y inputs/outputs can be interconnected by establishingappropriate patterns in the control memory. Alogical “1” on the RESET input will asynchronouslyreturn all memory locations to logical “0” turning offall crosspoint switches. Two voltage reference pins(VSS and VEE) are provided for the MT8808 toenable switching of negative analog signals. Therange for digital signals is from VDD to VSS while therange for analog signals is from VDD to VEE. Vand VSSEE pins can be tied together if a single voltagereference is needed.

ISO-CMOS

MT8808

Address Decode

The six address inputs along with the STROBE arelogically ANDed to form an enable signal for theresettable transparent latches. The DATA input isbuffered and is used as the input to all latches. Towrite to a location, RESET must be low while theaddress and data are set up. Then the STROBEinput is set high and then low causing the data to belatched. The data can be changed while STROBE ishigh, however, the corresponding switch will turn onand off in accordance with the DATA input. DATAmust be stable on the falling edge of STROBE inorder for correct data to be written to the latch.

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MT8808

ISO-CMOS

Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated.

Parameter

123456

Supply VoltageAnalog Input VoltageDigital Input VoltageCurrent on any I/O PinStorage TemperaturePackage Power Dissipation

PLASTIC DIPCERDIP

SymbolVDDVSSVINAVINITSPDPD

-65Min-0.3-0.3-0.3VSS-0.3

Max15.0VDD+0.3VDD+0.3VDD+0.3±15+1500.61.0

UnitsVVVVmA°CWW

*Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated.

Characteristics

1234

Operating TemperatureSupply VoltageAnalog Input VoltageDigital Input Voltage

SymTOVDDVSSVINAVIN

Min-404.5VEEVEEVSS

Typ25

Max8513.2VDD-4.5VDDVDD

Units°CVVVV

Test Conditions

DC Electrical Characteristics†- Voltages are with respect to VEE=VSS=0V, VDD =12V unless otherwise stated.

Characteristics

1

Quiescent Supply Current

SymIDD

Min

Typ‡10.45

23456

Off-state Leakage Current(See G.9 in Appendix)Input Logic “0” levelInput Logic “1” levelInput Logic “1” levelInput Leakage (digital pins)

IOFFVILVIHVIHILEAK

2.0+VSS

Max1001.515±500

0.8+VSS

UnitsµAmAmAnAVVV

Test Conditions

All digital inputs at VIN=VSS or VDD

All digital inputs at VIN=2.4 + VSS ; VSS =7.0V

All digital inputs at VIN=3.4VIVXi - VYjI = VDD - VEESee Appendix, Fig. A.1VSS =7.5V; VEE=0VVSS =6.5V; VEE=0V

All digital inputs at VIN = VSS or VDD

±1

3.3

0.1

10

µA

†DC Electrical Characteristics are over recommended temperature range.

‡Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.

DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.

Characteristics

Sym

25°CTyp

1On-stateVDD=12VResistanceVDD=10V

VDD= 5V

(See G.1, G.2, G.3 in Appendix)

RON

4555120

Max6575185

70°CTyp

Max7585215

85°CTyp

Max8090225

ΩΩΩ

VSS=VEE=0V,VDC=VDD/2,IVXi-VYjI = 0.4V

See Appendix, Fig. A.2

Units

Test Conditions

2Difference in on-state ∆RON

resistance between two switches

(See G.4 in Appendix)

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5101010Ω

VDD=12V, VSS=VEE=0, VDC=VDD/2,IVXi-VYjI = 0.4V

See Appendix, Fig. A.2

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ISO-CMOS

MT8808

AC Electrical Characteristics† - Crosspoint Performance-Voltages are with respect to VDD=5V, VSS=0V,

VEE=-7V, unless otherwise stated.

Characteristics

123

Switch I/O CapacitanceFeedthrough CapacitanceFrequency ResponseChannel “ON”

20LOG(VOUT/VXi)=-3dBTotal Harmonic Distortion(See G.5, G.6 in Appendix)Feedthrough Channel “OFF”

Feed.=20LOG (VOUT/VXi) (See G.8 in Appendix)

Crosstalk between any two channels for switches Xi-Yi and Xj-Yj.

Xtalk=20LOG (VYj/VXi).(See G.7 in Appendix).

SymCSCFF3dB

Min

Typ‡200.245

MaxUnitspFpFMHz

Test Conditionsf=1 MHzf=1 MHz

Switch is “ON”; VINA = 2Vpp sinewave; RL = 1kΩSee Appendix, Fig. A.3Switch is “ON”; VINA = 2Vpp sinewave f= 1kHz; RL=1kΩAll Switches “OFF”; VINA= 2Vpp sinewave f= 1kHz; RL= 1kΩ.

See Appendix, Fig. A.4VINA=2Vpp sinewave f= 10MHz; RL = 75Ω.VINA=2Vpp sinewavef= 10kHz; RL = 600Ω.VINA=2Vpp sinewave f= 10kHz; RL = 1kΩ.VINA=2Vpp sinewave f= 1kHz; RL = 10kΩ.

Refer to Appendix, Fig. A.5 for test circuit.RL=1kΩ; CL=50pF

45

THDFDT

0.01-95

%dB

6

Xtalk

-45-90-85-80

dBdBdBdB

7

Propagation delay through switch

tPS

30ns

†Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.

‡Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.

Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better.

AC Electrical Characteristics† - Control and I/O Timings- Voltages are with respect to VDD=5V, VSS=0V,

VEE=-7V, unless otherwise stated.

Characteristics

1

Control Input crosstalk to switch (for CS, DATA, STROBE, Address)

Digital Input CapacitanceSwitching Frequency

Setup Time DATA to STROBEHold Time DATA to STROBESetup Time Address to STROBEHold Time Address to STROBESTROBE Pulse WidthRESET Pulse Width

STROBE to Switch Status DelayDATA to Switch Status DelayRESET to Switch Status Delay

SymCXtalk

Min

Typ‡30

MaxUnitsmVpp

Test ConditionsVIN=3V squarewave;RIN=1kΩ, RL=10kΩ.See Appendix, Fig. A.6f=1MHz

RL= 1kΩ, CL=50pF QRL= 1kΩ, CL=50pF QRL= 1kΩ, CL=50pF QRL= 1kΩ, CL=50pF QRL= 1kΩ, CL=50pF QRL= 1kΩ, CL=50pF QRL= 1kΩ, CL=50pF QRL= 1kΩ, CL=50pF QRL= 1kΩ, CL=50pF Q

234567101112

CDIFOtDStDHtAStAHtSPWtRPWtStDtR

101010102040

10

20

pFMHznsnsnsnsnsns

405035

100100100

nsnsns

†Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5ns.

‡Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Q Refer to Appendix, Fig. A.7 for test circuit.

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MT8808

ISO-CMOS

tRPW50%tSPW50%tASADDRESS50%50%tAHDATA50%tDSONOFFtDtStRtRtDH50%50%50%50%RESETSTROBESWITCH*Figure 3 - Control Memory Timing Diagram*See Appendix, Fig. A.7 for switching waveform

AY2

00000000000000000000000000000000

AY1

00000000000000001111111111111111

AY0

00000000111111110000000011111111

AX2

00001111000011110000111100001111

AX1

00110011001100110011001100110011

AX0

01010101010101010101010101010101

Connection

X0 Y0X1 Y0X2 Y0X3 Y0X4 Y0X5 Y0X6 Y0X7 Y0X0 Y1X1 Y1X2 Y1X3 Y1X4 Y1X5 Y1X6 Y1X7 Y1X0 Y2X1 Y2X2 Y2X3 Y2X4 Y2X5 Y2X6 Y2X7 Y2X0 Y3X1 Y3X2 Y3X3 Y3X4 Y3X5 Y3X6 Y3X7 Y3

AY2

11111111111111111111111111111111

AY1

00000000000000001111111111111111

AY0

00000000111111110000000011111111

AX2

00001111000011110000111100001111

AX1

00110011001100110011001100110011

AX0

01010101010101010101010101010101

Connection

X0 Y4X1 Y4X2 Y4X3 Y4X4 Y4X5 Y4X6 Y4X7 Y4X0 Y5X1 Y5X2 Y5X3 Y5X4 Y5X5 Y5X6 Y5X7 Y5X0 Y6X1 Y6X2 Y6X3 Y6X4 Y6X5 Y6X6 Y6X7 Y6X0 Y7X1 Y7X2 Y7X3 Y7X4 Y7X5 Y7X6 Y7X7 Y7

Table 1. Address Decode Truth Table

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