S3C2410XPRODUCT OVERVIEW
INTRODUCTION
This manual describes SAMSUNG's S3C2410X 16/32-bit RISC microprocessor. This product is designed to
provide hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller solution in small die size. To reduce total system cost, the S3C2410X includes the following
components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management,LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM
Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch ScreenInterface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface,2-ch SPI and PLL for clock generation.
The S3C2410X was developed using an ARM920T core, 0.18um CMOS standard cells and a memory complier.Its low-power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitiveapplications. It adopts a new bus architecture called Advanced Microcontroller Bus Architecture (AMBA).The S3C2410X offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed byAdvanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecturewith separate 16KB instruction and 16KB data caches, each with an 8-word line length.
By providing a complete set of common system peripherals, the S3C2410X minimizes overall system costs andeliminates the need to configure additional components. The integrated on-chip functions that are described inthis document include:
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1.8V int., 3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-Cache/MMUExternal memory controller (SDRAM Control and Chip Select logic)
LCD controller (up to 4K color STN and 256K color TFT) with 1-ch LCD-dedicated DMA4-ch DMAs with external request pins
3-ch UART (IrDA1.0, 16-Byte Tx FIFO, and 16-Byte Rx FIFO) / 2-ch SPI
1-ch multi-master IIC-BUS/1-ch IIS-BUS controller
SD Host interface version 1.0 & Multi-Media Card Protocol version 2.11 compatible2-port USB Host /1- port USB Device (ver 1.1)4-ch PWM timers & 1-ch internal timer
Watch Dog Timer
117-bit general purpose I/O ports / 24-ch external interrupt sourcePower control: Normal, Slow, Idle and Power-off mode8-ch 10-bit ADC and Touch screen interfaceRTC with calendar function
On-chip clock generator with PLL
PRODUCT OVERVIEWS3C2410X
FEATURES
Architecture
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NAND Flash Boot Loader
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Integrated system for hand-held devices andgeneral embedded applications
16/32-Bit RISC architecture and powerfulinstruction set with ARM920T CPU coreEnhanced ARM architecture MMU to supportWinCE, EPOC 32 and Linux
Instruction cache, data cache, write buffer andPhysical address TAG RAM to reduce the effectof main memory bandwidth and latency onperformance
ARM920T CPU core supports the ARM debugarchitecture.
Internal Advanced Microcontroller Bus
Architecture (AMBA) (AMBA2.0, AHB/APB)
Supports booting from NAND flash memory4KB internal buffer for booting
Supports storage memory for NAND flashmemory after booting
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Cache Memory
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-way set-associative cache with I-Cache(16KB) and D-Cache (16KB)
8words length per line with one valid bit and twodirty bits per line
Pseudo random or round robin replacementalgorithm
Write-through or write-back cache operation toupdate the main memory
The write buffer can hold 16 words of data andfour addresses.
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System Manager
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Little/Big Endian support
Address space: 128M bytes for each bank (total1G bytes)
Supports programmable 8/16/32-bit data buswidth for each bank
Fixed bank start address from bank 0 to bank 6Programmable bank start address and bank sizefor bank 7
Eight memory banks:
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Clock & Power Manager
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On-chip MPLL and UPLL:
UPLL generates the clock to operate USBHost/Device.
MPLL generates the clock to operate MCU atmaximum 203Mhz @ 1.8V.
Clock can be fed selectively to each functionblock by software.
Power mode: Normal, Slow, Idle, and Power-offmode
Normal mode: Normal operating mode
Slow mode: Low frequency clock without PLLIdle mode: The clock for only CPU is stopped.Power-off mode: The Core power including allperipherals is shut down.
Woken up by EINT[15:0] or RTC alarm interruptfrom Power-Off mode
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–Six memory banks for ROM, SRAM, andothers.
–Two memory banks for ROM/SRAM/Synchronous DRAM
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Fully Programmable access cycles for allmemory banks
Supports external wait signals to expend the buscycle
Supports self-refresh mode in SDRAM for power-down
Supports various types of ROM for booting(NOR/NAND Flash, EEPROM, and others)
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S3C2410X PRODUCT OVERVIEW
Table 1-2. 272-Pin FBGA Pin Assignments (Sheet 8 of 9)
PinNumber
PinName
VSSMOPADDR18/GPA3ADDR19/GPA4ADDR20/GPA5ADDR21/GPA6ADDR22/GPA7ADDR23/GPA8ADDR24/GPA9ADDR25/GPA10ADDR26/GPA11VDDiVSSiVDDMOPVSSMOPDATA0DATA1DATA2DATA3DATA4DATA5DATA6DATA7VDDMOPVSSMOPDATA8DATA9DATA10DATA11DATA12DATA13DATA14DATA15VDDMOP
DefaultFunctionVSSMOPADDR18ADDR19ADDR20ADDR21ADDR22ADDR23ADDR24ADDR25ADDR26VDDiVSSiVDDMOPVSSMOPDATA0DATA1DATA2DATA3DATA4DATA5DATA6DATA7VDDMOPVSSMOPDATA8DATA9DATA10DATA11DATA12DATA13DATA14DATA15VDDMOP
I/O State@BUS REQ
PHi-z/–Hi-z/–Hi-z/–Hi-z/–Hi-z/–Hi-z/–Hi-z/–Hi-z/–Hi-z/–PPPPHi-zHi-zHi-zHi-zHi-zHi-zHi-zHi-zPPHi-zHi-zHi-zHi-zHi-zHi-zHi-zHi-zP
I/O State@PWR-off
PO(L)O(L)O(L)O(L)O(L)O(L)O(L)O(L)O(L)PPPPHi-zHi-zHi-zHi-zHi-zHi-zHi-zHi-zPPHi-zHi-zHi-zHi-zHi-zHi-zHi-zHi-zP
I/O State@nRESET
PO(L)O(L)O(L)O(L)O(L)O(L)O(L)O(L)O(L)PPPPHi-zHi-zHi-zHi-zHi-zHi-zHi-zHi-zPPHi-zHi-zHi-zHi-zHi-zHi-zHi-zHi-zP
I/OTypes3ootototototototototd1cs3id3os3ot12t12t12t12t12t12t12t12d3os3ot12t12t12t12t12t12t12t12d3o
C10E10D10F10A9D9E9B9C9E8C8F9D8G9B8A8D7E7C7B7A7C6A6F8F7B6D6A5C5B5D5A4B4
PRODUCT OVERVIEWS3C2410X
S3C2410X PRODUCT OVERVIEW
